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From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <u-boot@lists.denx.de>
Cc: <ycliang@andestech.com>, <rick@andestech.com>,
	Yu Chien Peter Lin <peterlin@andestech.com>
Subject: [PATCH 03/11] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
Date: Thu, 19 Jan 2023 15:05:36 +0800	[thread overview]
Message-ID: <20230119070544.7423-4-peterlin@andestech.com> (raw)
In-Reply-To: <20230119070544.7423-1-peterlin@andestech.com>

The L2-cache is not enabled currently, the enbale_caches() will call
the v5l2_enable() callback to enable it in SPL.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 63a966e092..1c2288b6ce 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <flash.h>
 #include <image.h>
 #include <init.h>
@@ -72,6 +73,14 @@ void *board_fdt_blob_setup(int *err)
 	return NULL;
 }
 
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init()
+{
+	/* enable v5l2 cache */
+	enable_caches();
+}
+#endif
+
 int smc_init(void)
 {
 	int node = -1;
@@ -96,18 +105,10 @@ int smc_init(void)
 	return 0;
 }
 
-static void v5l2_init(void)
-{
-	struct udevice *dev;
-
-	uclass_get_device(UCLASS_CACHE, 0, &dev);
-}
-
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
 	smc_init();
-	v5l2_init();
 
 	return 0;
 }
-- 
2.34.1


  parent reply	other threads:[~2023-01-19  7:06 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-19  7:05 [PATCH 00/11] cache operation cleanups for Andes AE350 platform Yu Chien Peter Lin
2023-01-19  7:05 ` [PATCH 01/11] riscv: global_data.h: Correct the comment for PLICSW Yu Chien Peter Lin
2023-01-31  6:39   ` Leo Liang
     [not found]   ` <PU1PR03MB2997857A35E6E20FAD5C032AC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01  3:37     ` Rick Chen
2023-01-19  7:05 ` [PATCH 02/11] riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" Yu Chien Peter Lin
2023-01-31  6:41   ` Leo Liang
     [not found]   ` <PU1PR03MB29972FC9DEB3F9F0889143BAC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01  5:20     ` Rick Chen
2023-01-19  7:05 ` Yu Chien Peter Lin [this message]
2023-01-31  6:59   ` [PATCH 03/11] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() Leo Liang
     [not found]   ` <PU1PR03MB29972FEA49428A23FA2D8786C1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01  5:23     ` Rick Chen
2023-01-19  7:05 ` [PATCH 04/11] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform Yu Chien Peter Lin
2023-01-31  7:01   ` Leo Liang
2023-01-19  7:05 ` [PATCH 05/11] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() Yu Chien Peter Lin
2023-01-31  7:07   ` Leo Liang
2023-01-31 15:49     ` Yu-Chien Peter Lin
2023-01-19  7:05 ` [PATCH 06/11] riscv: ae350: dts: Update L2 cache compatible string Yu Chien Peter Lin
2023-01-31  7:07   ` Leo Liang
2023-01-19  7:05 ` [PATCH 07/11] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL Yu Chien Peter Lin
2023-01-31  7:09   ` Leo Liang
2023-01-19  7:05 ` [PATCH 08/11] configs: ae350: Enable v5l2 cache for AE350 platforms Yu Chien Peter Lin
2023-01-31  7:17   ` Leo Liang
     [not found]   ` <PU1PR03MB299711E617F0F0969237426EC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01  5:32     ` Rick Chen
2023-01-19  7:05 ` [PATCH 09/11] configs: ae350: Increase maximum retry count " Yu Chien Peter Lin
2023-01-31  7:18   ` Leo Liang
2023-01-19  7:05 ` [PATCH 10/11] configs: ae350: Display CPU and board info " Yu Chien Peter Lin
2023-01-31  7:18   ` Leo Liang
2023-01-19  7:05 ` [PATCH 11/11] driver: cache-v5l2: Fix type casting warning on RV32 Yu Chien Peter Lin
2023-01-31  7:19   ` Leo Liang

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