From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <u-boot@lists.denx.de>
Cc: <ycliang@andestech.com>, <rick@andestech.com>,
Yu Chien Peter Lin <peterlin@andestech.com>
Subject: [PATCH 06/11] riscv: ae350: dts: Update L2 cache compatible string
Date: Thu, 19 Jan 2023 15:05:39 +0800 [thread overview]
Message-ID: <20230119070544.7423-7-peterlin@andestech.com> (raw)
In-Reply-To: <20230119070544.7423-1-peterlin@andestech.com>
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
arch/riscv/dts/ae350_32.dts | 2 +-
arch/riscv/dts/ae350_64.dts | 2 +-
drivers/cache/cache-v5l2.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 96ef8bd8dd..61af6d5465 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -112,7 +112,7 @@
};
L2: l2-cache@e0500000 {
- compatible = "v5l2cache";
+ compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0xe0500000 0x40000>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index cddbaec98a..8c7db29b4f 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -112,7 +112,7 @@
};
L2: l2-cache@e0500000 {
- compatible = "v5l2cache";
+ compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0x0 0xe0500000 0x0 0x40000>;
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
index e782430c57..c6d3a8f893 100644
--- a/drivers/cache/cache-v5l2.c
+++ b/drivers/cache/cache-v5l2.c
@@ -184,7 +184,7 @@ static int v5l2_probe(struct udevice *dev)
}
static const struct udevice_id v5l2_cache_ids[] = {
- { .compatible = "v5l2cache" },
+ { .compatible = "cache" },
{}
};
--
2.34.1
next prev parent reply other threads:[~2023-01-19 7:07 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-19 7:05 [PATCH 00/11] cache operation cleanups for Andes AE350 platform Yu Chien Peter Lin
2023-01-19 7:05 ` [PATCH 01/11] riscv: global_data.h: Correct the comment for PLICSW Yu Chien Peter Lin
2023-01-31 6:39 ` Leo Liang
[not found] ` <PU1PR03MB2997857A35E6E20FAD5C032AC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01 3:37 ` Rick Chen
2023-01-19 7:05 ` [PATCH 02/11] riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" Yu Chien Peter Lin
2023-01-31 6:41 ` Leo Liang
[not found] ` <PU1PR03MB29972FC9DEB3F9F0889143BAC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01 5:20 ` Rick Chen
2023-01-19 7:05 ` [PATCH 03/11] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() Yu Chien Peter Lin
2023-01-31 6:59 ` Leo Liang
[not found] ` <PU1PR03MB29972FEA49428A23FA2D8786C1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01 5:23 ` Rick Chen
2023-01-19 7:05 ` [PATCH 04/11] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform Yu Chien Peter Lin
2023-01-31 7:01 ` Leo Liang
2023-01-19 7:05 ` [PATCH 05/11] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() Yu Chien Peter Lin
2023-01-31 7:07 ` Leo Liang
2023-01-31 15:49 ` Yu-Chien Peter Lin
2023-01-19 7:05 ` Yu Chien Peter Lin [this message]
2023-01-31 7:07 ` [PATCH 06/11] riscv: ae350: dts: Update L2 cache compatible string Leo Liang
2023-01-19 7:05 ` [PATCH 07/11] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL Yu Chien Peter Lin
2023-01-31 7:09 ` Leo Liang
2023-01-19 7:05 ` [PATCH 08/11] configs: ae350: Enable v5l2 cache for AE350 platforms Yu Chien Peter Lin
2023-01-31 7:17 ` Leo Liang
[not found] ` <PU1PR03MB299711E617F0F0969237426EC1D19@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-01 5:32 ` Rick Chen
2023-01-19 7:05 ` [PATCH 09/11] configs: ae350: Increase maximum retry count " Yu Chien Peter Lin
2023-01-31 7:18 ` Leo Liang
2023-01-19 7:05 ` [PATCH 10/11] configs: ae350: Display CPU and board info " Yu Chien Peter Lin
2023-01-31 7:18 ` Leo Liang
2023-01-19 7:05 ` [PATCH 11/11] driver: cache-v5l2: Fix type casting warning on RV32 Yu Chien Peter Lin
2023-01-31 7:19 ` Leo Liang
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