From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A7B5C25B50 for ; Sat, 21 Jan 2023 15:55:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 15F8C856A7; Sat, 21 Jan 2023 16:55:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="i1lT3Zio"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7853E855D1; Sat, 21 Jan 2023 16:54:46 +0100 (CET) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AA82485678 for ; Sat, 21 Jan 2023 16:54:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjoerd@collabora.com Received: from beast.luon.net (simons.connected.by.freedominter.net [45.83.240.172]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sjoerd) by madras.collabora.co.uk (Postfix) with ESMTPSA id 350606602E10; Sat, 21 Jan 2023 15:54:42 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674316482; bh=N3sj9xa8gZGRPAdI9+YuPZDtOIkiXYL2ghZ8BLS6Bq0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i1lT3ZioVj0i27A4+UcZnLjUgzJAW+BEcRVvdZ0HHzqNhPPFTbdlPt8ZwR/DW4rO1 HtSySF8XC/oUuBXjuyZPhaEvcCRZ7sKW+4ohRf4RzWIzsPjabOdgrJh3Vf/UzhAUpw cyEqOd0m7ZJQcrTLEIe65/56sHn9OXU97dV5h6lKG/zuh5zT6WfSIbj8V9Eh9mMnvV ibQu7awR7mAWzJqr4fAzRFYrdfjPmPqKL8Qi5oQXh3ov6KxJUXO3MNAh2eS0eyQZHb jySvvJSM/yS58Ps9J+YFV55SmYnIQbmsSx9nIIqhb//j0fu38RgDDcIEIQ2mJVL9wR pqXD06bOQsU9w== Received: by beast.luon.net (Postfix, from userid 1000) id C3C5764481F1; Sat, 21 Jan 2023 16:54:39 +0100 (CET) From: Sjoerd Simons To: u-boot@lists.denx.de Cc: Angus Ainslie , Jan Kiszka , Marek Vasut , Michal Simek , Sean Anderson , T Karthik Reddy Subject: [PATCH 5/8] usb: dwc3: Add dwc3 glue for am62 Date: Sat, 21 Jan 2023 16:54:31 +0100 Message-Id: <20230121155435.2858173-6-sjoerd@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230121155435.2858173-1-sjoerd@collabora.com> References: <20230121155435.2858173-1-sjoerd@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add glue code for TI AM62 to the dwc3 driver; Most code adopted from TI vendor u-boot code. Signed-off-by: Sjoerd Simons --- drivers/usb/dwc3/dwc3-generic.c | 102 ++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 78966718d01..cab7b2e928d 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,7 +24,9 @@ #include #include "core.h" #include "gadget.h" +#include #include +#include #include #include #include @@ -398,6 +401,104 @@ struct dwc3_glue_ops ti_ops = { .glue_configure = dwc3_ti_glue_configure, }; +void dwc3_ti_am62_glue_configure(struct udevice *dev, int index, + enum usb_dr_mode mode) +{ +#define USBSS_MODE_CONTROL 0x1c +#define USBSS_PHY_CONFIG 0x8 +#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1) +#define USBSS_PHY_VBUS_SEL_SHIFT 1 +#define USBSS_MODE_VALID BIT(0) +#define PHY_PLL_REFCLK_MASK GENMASK(3, 0) +static const int dwc3_ti_am62_rate_table[] = { /* in KHZ */ + 9600, + 10000, + 12000, + 19200, + 20000, + 24000, + 25000, + 26000, + 38400, + 40000, + 58000, + 50000, + 52000, +}; + + struct clk usb2_refclk; + int rate_code, i, ret; + unsigned long rate; + u32 reg; + void *usbss; + bool vbus_divider; + struct regmap *syscon; + struct ofnode_phandle_args args; + + usbss = dev_remap_addr_index(dev, 0); + if (IS_ERR(usbss)) { + dev_err(dev, "can't map IOMEM resource\n"); + return; + } + + ret = clk_get_by_name(dev, "ref", &usb2_refclk); + if (ret) { + dev_err(dev, "can't get usb2_refclk\n"); + return; + } + + /* Calcuate the rate code */ + rate = clk_get_rate(&usb2_refclk); + rate /= 1000; /* To KHz */ + for (i = 0; i < ARRAY_SIZE(dwc3_ti_am62_rate_table); i++) { + if (dwc3_ti_am62_rate_table[i] == rate) + break; + } + + if (i == ARRAY_SIZE(dwc3_ti_am62_rate_table)) { + dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate); + return; + } + + rate_code = i; + + /* Read the syscon property */ + syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-phy-pll-refclk"); + if (IS_ERR(syscon)) { + dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n"); + return; + } + + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "ti,syscon-phy-pll-refclk", NULL, 1, + 0, &args); + if (ret) + return; + + /* Program PHY PLL refclk by reading syscon property */ + ret = regmap_update_bits(syscon, args.args[0], PHY_PLL_REFCLK_MASK, rate_code); + if (ret) { + dev_err(dev, "failed to set phy pll reference clock rate\n"); + return; + } + + /* VBUS divider select */ + reg = readl(usbss + USBSS_PHY_CONFIG); + vbus_divider = dev_read_bool(dev, "ti,vbus-divider"); + if (vbus_divider) + reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT; + + writel(reg, usbss + USBSS_PHY_CONFIG); + + /* Set mode valid */ + reg = readl(usbss + USBSS_MODE_CONTROL); + reg |= USBSS_MODE_VALID; + writel(reg, usbss + USBSS_MODE_CONTROL); +} + +struct dwc3_glue_ops ti_am62_ops = { + .glue_configure = dwc3_ti_am62_glue_configure, +}; + static int dwc3_glue_bind(struct udevice *parent) { ofnode node; @@ -570,6 +671,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,keystone-dwc3"}, { .compatible = "ti,dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops }, + { .compatible = "ti,am62-usb", .data = (ulong)&ti_am62_ops }, { .compatible = "ti,am654-dwc3" }, { .compatible = "rockchip,rk3328-dwc3" }, { .compatible = "rockchip,rk3399-dwc3" }, -- 2.39.0