From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2296C27C76 for ; Mon, 23 Jan 2023 00:49:52 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CAF848566F; Mon, 23 Jan 2023 01:49:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id ED3F684954; Mon, 23 Jan 2023 01:49:48 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 3E5AF8566F for ; Mon, 23 Jan 2023 01:49:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ECAA4AD7; Sun, 22 Jan 2023 16:50:26 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 235E13F5A1; Sun, 22 Jan 2023 16:49:44 -0800 (PST) Date: Mon, 23 Jan 2023 00:47:52 +0000 From: Andre Przywara To: Samuel Holland Cc: Jernej Skrabec , Anatolij Gustschin , Jagan Teki , Lukasz Majewski , Sean Anderson , u-boot@lists.denx.de Subject: Re: [PATCH 4/5] video: sunxi: dw-hdmi: Use DM for clock gates and resets Message-ID: <20230123004752.2414ae83@slackpad.lan> In-Reply-To: <20221128070229.4394-5-samuel@sholland.org> References: <20221128070229.4394-1-samuel@sholland.org> <20221128070229.4394-5-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Mon, 28 Nov 2022 01:02:27 -0600 Samuel Holland wrote: Hi, > This abstracts away the CCU register layout, which is necessary for > supporting new SoCs like H6 with a reorganized CCU. One of the resets is > referenced from the PHY node instead of the controller node, so it will > have to wait until the PHY code is factored out to a separate driver. > > Signed-off-by: Samuel Holland > --- > > drivers/video/sunxi/sunxi_dw_hdmi.c | 26 ++++++++++++++++++++------ > 1 file changed, 20 insertions(+), 6 deletions(-) > > diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c > index 4f5d0989286..04588b570fd 100644 > --- a/drivers/video/sunxi/sunxi_dw_hdmi.c > +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c > @@ -5,12 +5,14 @@ > * (C) Copyright 2017 Jernej Skrabec > */ > > +#include > #include > #include > #include > #include > #include > #include > +#include > #include > #include > #include > @@ -327,6 +329,8 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) > struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); > struct sunxi_ccm_reg * const ccm = > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > + struct reset_ctl_bulk resets; > + struct clk_bulk clocks; > int ret; > > /* Set pll3 to 297 MHz */ > @@ -336,14 +340,24 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) > clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, > CCM_HDMI_CTRL_PLL3); > > - /* Set ahb gating to pass */ > - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); > + /* This reset is referenced from the PHY devicetree node. */ > setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2); > - setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); > - setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE); > > - /* Clock on */ > - setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); > + ret = reset_get_bulk(dev, &resets); > + if (ret) > + return ret; > + > + ret = clk_get_bulk(dev, &clocks); > + if (ret) > + return ret; I understand that it complicates thing a bit, for little benefit, but shouldn't those two get operations be done in of_to_plat()? Cheers, Andre > + > + ret = reset_deassert_bulk(&resets); > + if (ret) > + return ret; > + > + ret = clk_enable_bulk(&clocks); > + if (ret) > + return ret; > > sunxi_dw_hdmi_phy_init(&priv->hdmi); >