[PATCH 0/5] video: sunxi: dw-hdmi: Partial OF conversion

[PATCH 0/5] video: sunxi: dw-hdmi: Partial OF conversion

[Samuel Holland]

This series starts converting the DE2 video driver to use devicetree for
MMIO addresses and clock/reset/regulator consumers. This is necessary
for adding new SoC support (H6, D1, etc.) and will also be helpful when
adding DSI output support.

I picked up a couple of patches from Jernej's branch and added a couple
on top. Specifically, the regulator consumer uses the AXP regulator
driver[1] (when enabled) to stop relying on TF-A.

I tested this series on a Pine A64 LTS board.

[1]: https://patchwork.ozlabs.org/project/uboot/cover/20221128064757.2933-1-samuel@sholland.org/


Jernej Skrabec (2):
  video: sunxi: dw-hdmi: Probe driver by compatible
  video: sunxi: dw-hdmi: Read address from DT node

Samuel Holland (3):
  clk: sunxi: Add DE2 display-related clocks/resets
  video: sunxi: dw-hdmi: Use DM for clock gates and resets
  video: sunxi: dw-hdmi: Use DM for HVCC regulator

 drivers/clk/sunxi/clk_a64.c         | 22 ++++++++
 drivers/clk/sunxi/clk_a83t.c        | 22 ++++++++
 drivers/clk/sunxi/clk_h3.c          | 17 ++++++
 drivers/clk/sunxi/clk_h6.c          | 21 +++++++
 drivers/clk/sunxi/clk_h616.c        | 21 +++++++
 drivers/clk/sunxi/clk_r40.c         | 29 ++++++++++
 drivers/clk/sunxi/clk_v3s.c         |  9 +++
 drivers/video/sunxi/sunxi_dw_hdmi.c | 87 +++++++++++++++++++----------
 8 files changed, 200 insertions(+), 28 deletions(-)

-- 
2.37.4

[PATCH 1/5] clk: sunxi: Add DE2 display-related clocks/resets

[Samuel Holland]

Add clock/reset definitions for display-related peripherals, including
the display engine, TCONs, and DSI and HDMI encoders, so those drivers
can be converted to DM clock consumers instead of directly manipulating
the CCU registers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/clk/sunxi/clk_a64.c  | 22 ++++++++++++++++++++++
 drivers/clk/sunxi/clk_a83t.c | 22 ++++++++++++++++++++++
 drivers/clk/sunxi/clk_h3.c   | 17 +++++++++++++++++
 drivers/clk/sunxi/clk_h6.c   | 21 +++++++++++++++++++++
 drivers/clk/sunxi/clk_h616.c | 21 +++++++++++++++++++++
 drivers/clk/sunxi/clk_r40.c  | 29 +++++++++++++++++++++++++++++
 drivers/clk/sunxi/clk_v3s.c  |  9 +++++++++
 7 files changed, 141 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 8c81b1ac453..136ba89293d 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -16,6 +16,7 @@
 static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_PLL_PERIPH0]	= GATE(0x028, BIT(31)),
 
+	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
@@ -28,6 +29,11 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_TCON0]		= GATE(0x064, BIT(3)),
+	[CLK_BUS_TCON1]		= GATE(0x064, BIT(4)),
+	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
+
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
 	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
@@ -48,6 +54,15 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
+
+	[CLK_DE]		= GATE(0x104, BIT(31)),
+	[CLK_TCON0]		= GATE(0x118, BIT(31)),
+	[CLK_TCON1]		= GATE(0x11c, BIT(31)),
+
+	[CLK_HDMI]		= GATE(0x150, BIT(31)),
+	[CLK_HDMI_DDC]		= GATE(0x154, BIT(31)),
+
+	[CLK_DSI_DPHY]		= GATE(0x168, BIT(15)),
 };
 
 static const struct ccu_reset a64_resets[] = {
@@ -55,6 +70,7 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
@@ -67,6 +83,12 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
 	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
 
+	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(3)),
+	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(4)),
+	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
+	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
+
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
 	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
 	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 3562da61d14..d5af37b3d78 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -14,6 +14,7 @@
 #include <linux/bitops.h>
 
 static struct ccu_clk_gate a83t_gates[] = {
+	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
@@ -25,6 +26,11 @@ static struct ccu_clk_gate a83t_gates[] = {
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_TCON0]		= GATE(0x064, BIT(4)),
+	[CLK_BUS_TCON1]		= GATE(0x064, BIT(5)),
+	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
+
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
 	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
@@ -44,6 +50,15 @@ static struct ccu_clk_gate a83t_gates[] = {
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
 	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+
+	[CLK_TCON0]		= GATE(0x118, BIT(31)),
+	[CLK_TCON1]		= GATE(0x11c, BIT(31)),
+
+	[CLK_HDMI]		= GATE(0x150, BIT(31)),
+	[CLK_HDMI_SLOW]		= GATE(0x154, BIT(31)),
+
+	[CLK_MIPI_DSI0]		= GATE(0x168, BIT(31)),
+	[CLK_MIPI_DSI1]		= GATE(0x16c, BIT(31)),
 };
 
 static struct ccu_reset a83t_resets[] = {
@@ -51,6 +66,7 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
@@ -62,6 +78,12 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
 
+	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(4)),
+	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(5)),
+	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
+	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
+
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
 	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
 	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 17ab3b5c278..213ab510ed5 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -32,6 +32,11 @@ static struct ccu_clk_gate h3_gates[] = {
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_TCON0]		= GATE(0x064, BIT(3)),
+	[CLK_BUS_TCON1]		= GATE(0x064, BIT(4)),
+	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
+
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
 	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
@@ -55,6 +60,12 @@ static struct ccu_clk_gate h3_gates[] = {
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
 	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
 	[CLK_USB_OHCI3]		= GATE(0x0cc, BIT(19)),
+
+	[CLK_DE]		= GATE(0x104, BIT(31)),
+	[CLK_TCON0]		= GATE(0x118, BIT(31)),
+
+	[CLK_HDMI]		= GATE(0x150, BIT(31)),
+	[CLK_HDMI_DDC]		= GATE(0x154, BIT(31)),
 };
 
 static struct ccu_reset h3_resets[] = {
@@ -79,6 +90,12 @@ static struct ccu_reset h3_resets[] = {
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
 
+	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(3)),
+	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(4)),
+	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
+	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
+
 	[RST_BUS_EPHY]		= RESET(0x2c8, BIT(2)),
 
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 041bc5e80ed..24eb9725dbc 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -18,6 +18,9 @@ static struct ccu_clk_gate h6_gates[] = {
 
 	[CLK_APB1]		= GATE_DUMMY,
 
+	[CLK_DE]		= GATE(0x600, BIT(31)),
+	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
+
 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
@@ -55,9 +58,21 @@ static struct ccu_clk_gate h6_gates[] = {
 	[CLK_BUS_XHCI]		= GATE(0xa8c, BIT(5)),
 	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
 	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+
+	[CLK_HDMI]		= GATE(0xb00, BIT(31)),
+	[CLK_HDMI_SLOW]		= GATE(0xb04, BIT(31)),
+	[CLK_HDMI_CEC]		= GATE(0xb10, BIT(31)),
+	[CLK_BUS_HDMI]		= GATE(0xb1c, BIT(0)),
+	[CLK_BUS_TCON_TOP]	= GATE(0xb5c, BIT(0)),
+	[CLK_TCON_LCD0]		= GATE(0xb60, BIT(31)),
+	[CLK_BUS_TCON_LCD0]	= GATE(0xb7c, BIT(0)),
+	[CLK_TCON_TV0]		= GATE(0xb80, BIT(31)),
+	[CLK_BUS_TCON_TV0]	= GATE(0xb9c, BIT(0)),
 };
 
 static struct ccu_reset h6_resets[] = {
+	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+
 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
 	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
@@ -89,6 +104,12 @@ static struct ccu_reset h6_resets[] = {
 	[RST_BUS_XHCI]		= RESET(0xa8c, BIT(21)),
 	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
 	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+
+	[RST_BUS_HDMI]		= RESET(0xb1c, BIT(16)),
+	[RST_BUS_HDMI_SUB]	= RESET(0xb1c, BIT(17)),
+	[RST_BUS_TCON_TOP]	= RESET(0xb5c, BIT(16)),
+	[RST_BUS_TCON_LCD0]	= RESET(0xb7c, BIT(16)),
+	[RST_BUS_TCON_TV0]	= RESET(0xb9c, BIT(16)),
 };
 
 const struct ccu_desc h6_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 964636d7281..88d6bf3420d 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -17,6 +17,9 @@ static struct ccu_clk_gate h616_gates[] = {
 
 	[CLK_APB1]		= GATE_DUMMY,
 
+	[CLK_DE]		= GATE(0x600, BIT(31)),
+	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
+
 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
@@ -64,9 +67,21 @@ static struct ccu_clk_gate h616_gates[] = {
 	[CLK_BUS_EHCI2]		= GATE(0xa8c, BIT(6)),
 	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
 	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+
+	[CLK_HDMI]		= GATE(0xb00, BIT(31)),
+	[CLK_HDMI_SLOW]		= GATE(0xb04, BIT(31)),
+	[CLK_HDMI_CEC]		= GATE(0xb10, BIT(31)),
+	[CLK_BUS_HDMI]		= GATE(0xb1c, BIT(0)),
+	[CLK_BUS_TCON_TOP]	= GATE(0xb5c, BIT(0)),
+	[CLK_TCON_TV0]		= GATE(0xb80, BIT(31)),
+	[CLK_TCON_TV1]		= GATE(0xb84, BIT(31)),
+	[CLK_BUS_TCON_TV0]	= GATE(0xb9c, BIT(0)),
+	[CLK_BUS_TCON_TV1]	= GATE(0xb9c, BIT(1)),
 };
 
 static struct ccu_reset h616_resets[] = {
+	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+
 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
 	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
@@ -107,6 +122,12 @@ static struct ccu_reset h616_resets[] = {
 	[RST_BUS_EHCI2]		= RESET(0xa8c, BIT(22)),
 	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
 	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+
+	[RST_BUS_HDMI]		= RESET(0xb1c, BIT(16)),
+	[RST_BUS_HDMI_SUB]	= RESET(0xb1c, BIT(17)),
+	[RST_BUS_TCON_TOP]	= RESET(0xb5c, BIT(16)),
+	[RST_BUS_TCON_TV0]	= RESET(0xb9c, BIT(16)),
+	[RST_BUS_TCON_TV1]	= RESET(0xb9c, BIT(17)),
 };
 
 const struct ccu_desc h616_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index ef743d65b7f..630e80d2b4e 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -14,6 +14,7 @@
 #include <linux/bitops.h>
 
 static struct ccu_clk_gate r40_gates[] = {
+	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
@@ -30,7 +31,15 @@ static struct ccu_clk_gate r40_gates[] = {
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_HDMI0]		= GATE(0x064, BIT(10)),
+	[CLK_BUS_HDMI1]		= GATE(0x064, BIT(11)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
 	[CLK_BUS_GMAC]		= GATE(0x064, BIT(17)),
+	[CLK_BUS_TCON_LCD0]	= GATE(0x064, BIT(26)),
+	[CLK_BUS_TCON_LCD1]	= GATE(0x064, BIT(27)),
+	[CLK_BUS_TCON_TV0]	= GATE(0x064, BIT(28)),
+	[CLK_BUS_TCON_TV1]	= GATE(0x064, BIT(29)),
+	[CLK_BUS_TCON_TOP]	= GATE(0x064, BIT(30)),
 
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
@@ -59,6 +68,17 @@ static struct ccu_clk_gate r40_gates[] = {
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
 	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
+
+	[CLK_DE]		= GATE(0x104, BIT(31)),
+	[CLK_TCON_LCD0]		= GATE(0x110, BIT(31)),
+	[CLK_TCON_LCD1]		= GATE(0x114, BIT(31)),
+	[CLK_TCON_TV0]		= GATE(0x118, BIT(31)),
+	[CLK_TCON_TV1]		= GATE(0x11c, BIT(31)),
+
+	[CLK_HDMI]		= GATE(0x150, BIT(31)),
+	[CLK_HDMI_SLOW]		= GATE(0x154, BIT(31)),
+
+	[CLK_DSI_DPHY]		= GATE(0x168, BIT(15)),
 };
 
 static struct ccu_reset r40_resets[] = {
@@ -66,6 +86,7 @@ static struct ccu_reset r40_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 
+	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
@@ -82,7 +103,15 @@ static struct ccu_reset r40_resets[] = {
 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
 
+	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
+	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
 	[RST_BUS_GMAC]		= RESET(0x2c4, BIT(17)),
+	[RST_BUS_TCON_LCD0]	= RESET(0x2c4, BIT(26)),
+	[RST_BUS_TCON_LCD1]	= RESET(0x2c4, BIT(27)),
+	[RST_BUS_TCON_TV0]	= RESET(0x2c4, BIT(28)),
+	[RST_BUS_TCON_TV1]	= RESET(0x2c4, BIT(29)),
+	[RST_BUS_TCON_TOP]	= RESET(0x2c4, BIT(30)),
 
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
 	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index f2fd11eac2c..6524c13540e 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -20,6 +20,9 @@ static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 
+	[CLK_BUS_TCON0]		= GATE(0x064, BIT(4)),
+	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
+
 	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
 
 	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
@@ -31,6 +34,9 @@ static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 
 	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
+
+	[CLK_DE]		= GATE(0x104, BIT(31)),
+	[CLK_TCON0]		= GATE(0x118, BIT(31)),
 };
 
 static struct ccu_reset v3s_resets[] = {
@@ -42,6 +48,9 @@ static struct ccu_reset v3s_resets[] = {
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 
+	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(4)),
+	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
+
 	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
 	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
-- 
2.37.4

[PATCH 2/5] video: sunxi: dw-hdmi: Probe driver by compatible

[Samuel Holland]

From: Jernej Skrabec <jernej.skrabec@gmail.com>

Currently the sunxi dw-hdmi driver is probed unconditionally,
even if there is no such device.

Switch the driver to probing via a compatible string. This brings many
benefits; the driver is only probed when needed, and now it can read the
DT node.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/video/sunxi/sunxi_dw_hdmi.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 19ed80b48a4..e7265af7d8f 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -370,14 +370,16 @@ static const struct dm_display_ops sunxi_dw_hdmi_ops = {
 	.mode_valid = sunxi_dw_hdmi_mode_valid,
 };
 
-U_BOOT_DRIVER(sunxi_dw_hdmi) = {
-	.name	= "sunxi_dw_hdmi",
-	.id	= UCLASS_DISPLAY,
-	.ops	= &sunxi_dw_hdmi_ops,
-	.probe	= sunxi_dw_hdmi_probe,
-	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
+static const struct udevice_id sunxi_dw_hdmi_ids[] = {
+	{ .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
+	{ }
 };
 
-U_BOOT_DRVINFO(sunxi_dw_hdmi) = {
-	.name = "sunxi_dw_hdmi"
+U_BOOT_DRIVER(sunxi_dw_hdmi) = {
+	.name		= "sunxi_dw_hdmi",
+	.id		= UCLASS_DISPLAY,
+	.of_match	= sunxi_dw_hdmi_ids,
+	.probe		= sunxi_dw_hdmi_probe,
+	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
+	.ops		= &sunxi_dw_hdmi_ops,
 };
-- 
2.37.4

[PATCH 3/5] video: sunxi: dw-hdmi: Read address from DT node

[Samuel Holland]

From: Jernej Skrabec <jernej.skrabec@gmail.com>

Currently HDMI controller MMIO address is hardcoded. Change that so
address is read from DT node. That will make adding support for new
variants a bit easier.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/video/sunxi/sunxi_dw_hdmi.c | 39 ++++++++++++++++++-----------
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index e7265af7d8f..4f5d0989286 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -56,10 +56,10 @@ static int sunxi_dw_hdmi_get_divider(uint clock)
 		return 1;
 }
 
-static void sunxi_dw_hdmi_phy_init(void)
+static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 {
 	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
 	unsigned long tmo;
 	u32 tmp;
 
@@ -113,10 +113,10 @@ static void sunxi_dw_hdmi_phy_init(void)
 	writel(0x42494E47, &phy->unscramble);
 }
 
-static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
+static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
 {
 	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
 	int div = sunxi_dw_hdmi_get_divider(clock);
 	u32 tmp;
 
@@ -270,7 +270,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
 	int phy_div;
 
 	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
-	sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
+	sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
 
 	return 0;
 }
@@ -291,10 +291,10 @@ static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 				const struct display_timing *edid)
 {
+	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+		(struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
 	struct display_plat *uc_plat = dev_get_uclass_plat(dev);
-	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 	int ret;
 
 	ret = dw_hdmi_enable(&priv->hdmi, edid);
@@ -316,7 +316,7 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 	 * again or othwerwise BSP driver won't work. Dummy read is
 	 * needed or otherwise last write doesn't get written correctly.
 	 */
-	(void)readb(SUNXI_HDMI_BASE);
+	(void)readb(priv->hdmi.ioaddr);
 	writel(0, &phy->unscramble);
 
 	return 0;
@@ -345,13 +345,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
 	/* Clock on */
 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 
-	sunxi_dw_hdmi_phy_init();
-
-	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
-	priv->hdmi.i2c_clk_high = 0xd8;
-	priv->hdmi.i2c_clk_low = 0xfe;
-	priv->hdmi.reg_io_width = 1;
-	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
+	sunxi_dw_hdmi_phy_init(&priv->hdmi);
 
 	ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
 	if (ret < 0) {
@@ -364,6 +358,20 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
 	return 0;
 }
 
+static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
+{
+	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
+	struct dw_hdmi *hdmi = &priv->hdmi;
+
+	hdmi->ioaddr = (ulong)dev_read_addr(dev);
+	hdmi->i2c_clk_high = 0xd8;
+	hdmi->i2c_clk_low = 0xfe;
+	hdmi->reg_io_width = 1;
+	hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
+
+	return 0;
+}
+
 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
 	.read_edid = sunxi_dw_hdmi_read_edid,
 	.enable = sunxi_dw_hdmi_enable,
@@ -380,6 +388,7 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = {
 	.id		= UCLASS_DISPLAY,
 	.of_match	= sunxi_dw_hdmi_ids,
 	.probe		= sunxi_dw_hdmi_probe,
+	.of_to_plat	= sunxi_dw_hdmi_of_to_plat,
 	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
 	.ops		= &sunxi_dw_hdmi_ops,
 };
-- 
2.37.4

[PATCH 4/5] video: sunxi: dw-hdmi: Use DM for clock gates and resets

[Samuel Holland]

This abstracts away the CCU register layout, which is necessary for
supporting new SoCs like H6 with a reorganized CCU. One of the resets is
referenced from the PHY node instead of the controller node, so it will
have to wait until the PHY code is factored out to a separate driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/video/sunxi/sunxi_dw_hdmi.c | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 4f5d0989286..04588b570fd 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -5,12 +5,14 @@
  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  */
 
+#include <clk.h>
 #include <common.h>
 #include <display.h>
 #include <dm.h>
 #include <dw_hdmi.h>
 #include <edid.h>
 #include <log.h>
+#include <reset.h>
 #include <time.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -327,6 +329,8 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
 	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct reset_ctl_bulk resets;
+	struct clk_bulk clocks;
 	int ret;
 
 	/* Set pll3 to 297 MHz */
@@ -336,14 +340,24 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
 	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
 			CCM_HDMI_CTRL_PLL3);
 
-	/* Set ahb gating to pass */
-	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+	/* This reset is referenced from the PHY devicetree node. */
 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
-	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
 
-	/* Clock on */
-	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
+	ret = reset_get_bulk(dev, &resets);
+	if (ret)
+		return ret;
+
+	ret = clk_get_bulk(dev, &clocks);
+	if (ret)
+		return ret;
+
+	ret = reset_deassert_bulk(&resets);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&clocks);
+	if (ret)
+		return ret;
 
 	sunxi_dw_hdmi_phy_init(&priv->hdmi);
 
-- 
2.37.4

[PATCH 5/5] video: sunxi: dw-hdmi: Use DM for HVCC regulator

[Samuel Holland]

The HDMI PHY depends on the HVCC supply being enabled. So far we have
relied on it being enabled by an earlier firmware stage (SPL or TF-A).
Attempt to enable the regulator here, so we can remove that dependency.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/video/sunxi/sunxi_dw_hdmi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 04588b570fd..963689358a6 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -19,6 +19,7 @@
 #include <asm/arch/lcdc.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <power/regulator.h>
 
 struct sunxi_dw_hdmi_priv {
 	struct dw_hdmi hdmi;
@@ -331,8 +332,13 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct reset_ctl_bulk resets;
 	struct clk_bulk clocks;
+	struct udevice *hvcc;
 	int ret;
 
+	ret = device_get_supply_regulator(dev, "hvcc-supply", &hvcc);
+	if (!ret)
+		regulator_set_enable(hvcc, true);
+
 	/* Set pll3 to 297 MHz */
 	clock_set_pll3(297000000);
 
-- 
2.37.4

Re: [PATCH 0/5] video: sunxi: dw-hdmi: Partial OF conversion

[Jernej Škrabec]

Hi Samuel!

Dne ponedeljek, 28. november 2022 ob 08:02:23 CET je Samuel Holland 
napisal(a):
> This series starts converting the DE2 video driver to use devicetree for
> MMIO addresses and clock/reset/regulator consumers. This is necessary
> for adding new SoC support (H6, D1, etc.) and will also be helpful when
> adding DSI output support.
> 
> I picked up a couple of patches from Jernej's branch and added a couple
> on top. Specifically, the regulator consumer uses the AXP regulator
> driver[1] (when enabled) to stop relying on TF-A.
> 
> I tested this series on a Pine A64 LTS board.
> 
> [1]:
> https://patchwork.ozlabs.org/project/uboot/cover/20221128064757.2933-1-samu
> el@sholland.org/
> 
> 
> Jernej Skrabec (2):
>   video: sunxi: dw-hdmi: Probe driver by compatible
>   video: sunxi: dw-hdmi: Read address from DT node
> 
> Samuel Holland (3):
>   clk: sunxi: Add DE2 display-related clocks/resets
>   video: sunxi: dw-hdmi: Use DM for clock gates and resets
>   video: sunxi: dw-hdmi: Use DM for HVCC regulator

Thanks for working on this!

Whole series is
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

> 
>  drivers/clk/sunxi/clk_a64.c         | 22 ++++++++
>  drivers/clk/sunxi/clk_a83t.c        | 22 ++++++++
>  drivers/clk/sunxi/clk_h3.c          | 17 ++++++
>  drivers/clk/sunxi/clk_h6.c          | 21 +++++++
>  drivers/clk/sunxi/clk_h616.c        | 21 +++++++
>  drivers/clk/sunxi/clk_r40.c         | 29 ++++++++++
>  drivers/clk/sunxi/clk_v3s.c         |  9 +++
>  drivers/video/sunxi/sunxi_dw_hdmi.c | 87 +++++++++++++++++++----------
>  8 files changed, 200 insertions(+), 28 deletions(-)

Re: [PATCH 1/5] clk: sunxi: Add DE2 display-related clocks/resets

[Andre Przywara]

On Mon, 28 Nov 2022 01:02:24 -0600
Samuel Holland <samuel@sholland.org> wrote:

Hi,

> Add clock/reset definitions for display-related peripherals, including
> the display engine, TCONs, and DSI and HDMI encoders, so those drivers
> can be converted to DM clock consumers instead of directly manipulating
> the CCU registers.

Thanks for that. Compared all register addresses and bit locations
against their respective manual.

> Signed-off-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
>  drivers/clk/sunxi/clk_a64.c  | 22 ++++++++++++++++++++++
>  drivers/clk/sunxi/clk_a83t.c | 22 ++++++++++++++++++++++
>  drivers/clk/sunxi/clk_h3.c   | 17 +++++++++++++++++
>  drivers/clk/sunxi/clk_h6.c   | 21 +++++++++++++++++++++
>  drivers/clk/sunxi/clk_h616.c | 21 +++++++++++++++++++++
>  drivers/clk/sunxi/clk_r40.c  | 29 +++++++++++++++++++++++++++++
>  drivers/clk/sunxi/clk_v3s.c  |  9 +++++++++
>  7 files changed, 141 insertions(+)
> 
> diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
> index 8c81b1ac453..136ba89293d 100644
> --- a/drivers/clk/sunxi/clk_a64.c
> +++ b/drivers/clk/sunxi/clk_a64.c
> @@ -16,6 +16,7 @@
>  static const struct ccu_clk_gate a64_gates[] = {
>  	[CLK_PLL_PERIPH0]	= GATE(0x028, BIT(31)),
>  
> +	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
>  	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
>  	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
>  	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
> @@ -28,6 +29,11 @@ static const struct ccu_clk_gate a64_gates[] = {
>  	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
>  	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
>  
> +	[CLK_BUS_TCON0]		= GATE(0x064, BIT(3)),
> +	[CLK_BUS_TCON1]		= GATE(0x064, BIT(4)),
> +	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
> +	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
> +
>  	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
>  
>  	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
> @@ -48,6 +54,15 @@ static const struct ccu_clk_gate a64_gates[] = {
>  	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
>  	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
>  	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
> +
> +	[CLK_DE]		= GATE(0x104, BIT(31)),
> +	[CLK_TCON0]		= GATE(0x118, BIT(31)),
> +	[CLK_TCON1]		= GATE(0x11c, BIT(31)),
> +
> +	[CLK_HDMI]		= GATE(0x150, BIT(31)),
> +	[CLK_HDMI_DDC]		= GATE(0x154, BIT(31)),
> +
> +	[CLK_DSI_DPHY]		= GATE(0x168, BIT(15)),
>  };
>  
>  static const struct ccu_reset a64_resets[] = {
> @@ -55,6 +70,7 @@ static const struct ccu_reset a64_resets[] = {
>  	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
>  	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
>  
> +	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
>  	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
>  	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
>  	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
> @@ -67,6 +83,12 @@ static const struct ccu_reset a64_resets[] = {
>  	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
>  	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
>  
> +	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(3)),
> +	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(4)),
> +	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
> +	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
> +	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
> +
>  	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
>  	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
>  	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
> index 3562da61d14..d5af37b3d78 100644
> --- a/drivers/clk/sunxi/clk_a83t.c
> +++ b/drivers/clk/sunxi/clk_a83t.c
> @@ -14,6 +14,7 @@
>  #include <linux/bitops.h>
>  
>  static struct ccu_clk_gate a83t_gates[] = {
> +	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
>  	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
>  	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
>  	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
> @@ -25,6 +26,11 @@ static struct ccu_clk_gate a83t_gates[] = {
>  	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
>  	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
>  
> +	[CLK_BUS_TCON0]		= GATE(0x064, BIT(4)),
> +	[CLK_BUS_TCON1]		= GATE(0x064, BIT(5)),
> +	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
> +	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
> +
>  	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
>  
>  	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
> @@ -44,6 +50,15 @@ static struct ccu_clk_gate a83t_gates[] = {
>  	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
>  	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
>  	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
> +
> +	[CLK_TCON0]		= GATE(0x118, BIT(31)),
> +	[CLK_TCON1]		= GATE(0x11c, BIT(31)),
> +
> +	[CLK_HDMI]		= GATE(0x150, BIT(31)),
> +	[CLK_HDMI_SLOW]		= GATE(0x154, BIT(31)),
> +
> +	[CLK_MIPI_DSI0]		= GATE(0x168, BIT(31)),
> +	[CLK_MIPI_DSI1]		= GATE(0x16c, BIT(31)),
>  };
>  
>  static struct ccu_reset a83t_resets[] = {
> @@ -51,6 +66,7 @@ static struct ccu_reset a83t_resets[] = {
>  	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
>  	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
>  
> +	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
>  	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
>  	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
>  	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
> @@ -62,6 +78,12 @@ static struct ccu_reset a83t_resets[] = {
>  	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
>  	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
>  
> +	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(4)),
> +	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(5)),
> +	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
> +	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
> +	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
> +
>  	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
>  	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
>  	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
> index 17ab3b5c278..213ab510ed5 100644
> --- a/drivers/clk/sunxi/clk_h3.c
> +++ b/drivers/clk/sunxi/clk_h3.c
> @@ -32,6 +32,11 @@ static struct ccu_clk_gate h3_gates[] = {
>  	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
>  	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
>  
> +	[CLK_BUS_TCON0]		= GATE(0x064, BIT(3)),
> +	[CLK_BUS_TCON1]		= GATE(0x064, BIT(4)),
> +	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
> +	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
> +
>  	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
>  
>  	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
> @@ -55,6 +60,12 @@ static struct ccu_clk_gate h3_gates[] = {
>  	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
>  	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
>  	[CLK_USB_OHCI3]		= GATE(0x0cc, BIT(19)),
> +
> +	[CLK_DE]		= GATE(0x104, BIT(31)),
> +	[CLK_TCON0]		= GATE(0x118, BIT(31)),
> +
> +	[CLK_HDMI]		= GATE(0x150, BIT(31)),
> +	[CLK_HDMI_DDC]		= GATE(0x154, BIT(31)),
>  };
>  
>  static struct ccu_reset h3_resets[] = {
> @@ -79,6 +90,12 @@ static struct ccu_reset h3_resets[] = {
>  	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
>  	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
>  
> +	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(3)),
> +	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(4)),
> +	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
> +	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
> +	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
> +
>  	[RST_BUS_EPHY]		= RESET(0x2c8, BIT(2)),
>  
>  	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
> index 041bc5e80ed..24eb9725dbc 100644
> --- a/drivers/clk/sunxi/clk_h6.c
> +++ b/drivers/clk/sunxi/clk_h6.c
> @@ -18,6 +18,9 @@ static struct ccu_clk_gate h6_gates[] = {
>  
>  	[CLK_APB1]		= GATE_DUMMY,
>  
> +	[CLK_DE]		= GATE(0x600, BIT(31)),
> +	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
> +
>  	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
>  	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
>  	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
> @@ -55,9 +58,21 @@ static struct ccu_clk_gate h6_gates[] = {
>  	[CLK_BUS_XHCI]		= GATE(0xa8c, BIT(5)),
>  	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
>  	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
> +
> +	[CLK_HDMI]		= GATE(0xb00, BIT(31)),
> +	[CLK_HDMI_SLOW]		= GATE(0xb04, BIT(31)),
> +	[CLK_HDMI_CEC]		= GATE(0xb10, BIT(31)),
> +	[CLK_BUS_HDMI]		= GATE(0xb1c, BIT(0)),
> +	[CLK_BUS_TCON_TOP]	= GATE(0xb5c, BIT(0)),
> +	[CLK_TCON_LCD0]		= GATE(0xb60, BIT(31)),
> +	[CLK_BUS_TCON_LCD0]	= GATE(0xb7c, BIT(0)),
> +	[CLK_TCON_TV0]		= GATE(0xb80, BIT(31)),
> +	[CLK_BUS_TCON_TV0]	= GATE(0xb9c, BIT(0)),
>  };
>  
>  static struct ccu_reset h6_resets[] = {
> +	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
> +
>  	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
>  	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
>  	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
> @@ -89,6 +104,12 @@ static struct ccu_reset h6_resets[] = {
>  	[RST_BUS_XHCI]		= RESET(0xa8c, BIT(21)),
>  	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
>  	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
> +
> +	[RST_BUS_HDMI]		= RESET(0xb1c, BIT(16)),
> +	[RST_BUS_HDMI_SUB]	= RESET(0xb1c, BIT(17)),
> +	[RST_BUS_TCON_TOP]	= RESET(0xb5c, BIT(16)),
> +	[RST_BUS_TCON_LCD0]	= RESET(0xb7c, BIT(16)),
> +	[RST_BUS_TCON_TV0]	= RESET(0xb9c, BIT(16)),
>  };
>  
>  const struct ccu_desc h6_ccu_desc = {
> diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
> index 964636d7281..88d6bf3420d 100644
> --- a/drivers/clk/sunxi/clk_h616.c
> +++ b/drivers/clk/sunxi/clk_h616.c
> @@ -17,6 +17,9 @@ static struct ccu_clk_gate h616_gates[] = {
>  
>  	[CLK_APB1]		= GATE_DUMMY,
>  
> +	[CLK_DE]		= GATE(0x600, BIT(31)),
> +	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
> +
>  	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
>  	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
>  	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
> @@ -64,9 +67,21 @@ static struct ccu_clk_gate h616_gates[] = {
>  	[CLK_BUS_EHCI2]		= GATE(0xa8c, BIT(6)),
>  	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
>  	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
> +
> +	[CLK_HDMI]		= GATE(0xb00, BIT(31)),
> +	[CLK_HDMI_SLOW]		= GATE(0xb04, BIT(31)),
> +	[CLK_HDMI_CEC]		= GATE(0xb10, BIT(31)),
> +	[CLK_BUS_HDMI]		= GATE(0xb1c, BIT(0)),
> +	[CLK_BUS_TCON_TOP]	= GATE(0xb5c, BIT(0)),
> +	[CLK_TCON_TV0]		= GATE(0xb80, BIT(31)),
> +	[CLK_TCON_TV1]		= GATE(0xb84, BIT(31)),
> +	[CLK_BUS_TCON_TV0]	= GATE(0xb9c, BIT(0)),
> +	[CLK_BUS_TCON_TV1]	= GATE(0xb9c, BIT(1)),
>  };
>  
>  static struct ccu_reset h616_resets[] = {
> +	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
> +
>  	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
>  	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
>  	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
> @@ -107,6 +122,12 @@ static struct ccu_reset h616_resets[] = {
>  	[RST_BUS_EHCI2]		= RESET(0xa8c, BIT(22)),
>  	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
>  	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
> +
> +	[RST_BUS_HDMI]		= RESET(0xb1c, BIT(16)),
> +	[RST_BUS_HDMI_SUB]	= RESET(0xb1c, BIT(17)),
> +	[RST_BUS_TCON_TOP]	= RESET(0xb5c, BIT(16)),
> +	[RST_BUS_TCON_TV0]	= RESET(0xb9c, BIT(16)),
> +	[RST_BUS_TCON_TV1]	= RESET(0xb9c, BIT(17)),
>  };
>  
>  const struct ccu_desc h616_ccu_desc = {
> diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
> index ef743d65b7f..630e80d2b4e 100644
> --- a/drivers/clk/sunxi/clk_r40.c
> +++ b/drivers/clk/sunxi/clk_r40.c
> @@ -14,6 +14,7 @@
>  #include <linux/bitops.h>
>  
>  static struct ccu_clk_gate r40_gates[] = {
> +	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
>  	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
>  	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
>  	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
> @@ -30,7 +31,15 @@ static struct ccu_clk_gate r40_gates[] = {
>  	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
>  	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
>  
> +	[CLK_BUS_HDMI0]		= GATE(0x064, BIT(10)),
> +	[CLK_BUS_HDMI1]		= GATE(0x064, BIT(11)),
> +	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
>  	[CLK_BUS_GMAC]		= GATE(0x064, BIT(17)),
> +	[CLK_BUS_TCON_LCD0]	= GATE(0x064, BIT(26)),
> +	[CLK_BUS_TCON_LCD1]	= GATE(0x064, BIT(27)),
> +	[CLK_BUS_TCON_TV0]	= GATE(0x064, BIT(28)),
> +	[CLK_BUS_TCON_TV1]	= GATE(0x064, BIT(29)),
> +	[CLK_BUS_TCON_TOP]	= GATE(0x064, BIT(30)),
>  
>  	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
>  
> @@ -59,6 +68,17 @@ static struct ccu_clk_gate r40_gates[] = {
>  	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
>  	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
>  	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
> +
> +	[CLK_DE]		= GATE(0x104, BIT(31)),
> +	[CLK_TCON_LCD0]		= GATE(0x110, BIT(31)),
> +	[CLK_TCON_LCD1]		= GATE(0x114, BIT(31)),
> +	[CLK_TCON_TV0]		= GATE(0x118, BIT(31)),
> +	[CLK_TCON_TV1]		= GATE(0x11c, BIT(31)),
> +
> +	[CLK_HDMI]		= GATE(0x150, BIT(31)),
> +	[CLK_HDMI_SLOW]		= GATE(0x154, BIT(31)),
> +
> +	[CLK_DSI_DPHY]		= GATE(0x168, BIT(15)),
>  };
>  
>  static struct ccu_reset r40_resets[] = {
> @@ -66,6 +86,7 @@ static struct ccu_reset r40_resets[] = {
>  	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
>  	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
>  
> +	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
>  	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
>  	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
>  	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
> @@ -82,7 +103,15 @@ static struct ccu_reset r40_resets[] = {
>  	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
>  	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
>  
> +	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
> +	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
> +	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
>  	[RST_BUS_GMAC]		= RESET(0x2c4, BIT(17)),
> +	[RST_BUS_TCON_LCD0]	= RESET(0x2c4, BIT(26)),
> +	[RST_BUS_TCON_LCD1]	= RESET(0x2c4, BIT(27)),
> +	[RST_BUS_TCON_TV0]	= RESET(0x2c4, BIT(28)),
> +	[RST_BUS_TCON_TV1]	= RESET(0x2c4, BIT(29)),
> +	[RST_BUS_TCON_TOP]	= RESET(0x2c4, BIT(30)),
>  
>  	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
>  	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
> diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
> index f2fd11eac2c..6524c13540e 100644
> --- a/drivers/clk/sunxi/clk_v3s.c
> +++ b/drivers/clk/sunxi/clk_v3s.c
> @@ -20,6 +20,9 @@ static struct ccu_clk_gate v3s_gates[] = {
>  	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
>  	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
>  
> +	[CLK_BUS_TCON0]		= GATE(0x064, BIT(4)),
> +	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
> +
>  	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
>  
>  	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
> @@ -31,6 +34,9 @@ static struct ccu_clk_gate v3s_gates[] = {
>  	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
>  
>  	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
> +
> +	[CLK_DE]		= GATE(0x104, BIT(31)),
> +	[CLK_TCON0]		= GATE(0x118, BIT(31)),
>  };
>  
>  static struct ccu_reset v3s_resets[] = {
> @@ -42,6 +48,9 @@ static struct ccu_reset v3s_resets[] = {
>  	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
>  	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
>  
> +	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(4)),
> +	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
> +
>  	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
>  	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
>  	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),

Re: [PATCH 2/5] video: sunxi: dw-hdmi: Probe driver by compatible

[Andre Przywara]

On Mon, 28 Nov 2022 01:02:25 -0600
Samuel Holland <samuel@sholland.org> wrote:

> From: Jernej Skrabec <jernej.skrabec@gmail.com>
> 
> Currently the sunxi dw-hdmi driver is probed unconditionally,
> even if there is no such device.
> 
> Switch the driver to probing via a compatible string. This brings many
> benefits; the driver is only probed when needed, and now it can read the
> DT node.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
>  drivers/video/sunxi/sunxi_dw_hdmi.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
> index 19ed80b48a4..e7265af7d8f 100644
> --- a/drivers/video/sunxi/sunxi_dw_hdmi.c
> +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
> @@ -370,14 +370,16 @@ static const struct dm_display_ops sunxi_dw_hdmi_ops = {
>  	.mode_valid = sunxi_dw_hdmi_mode_valid,
>  };
>  
> -U_BOOT_DRIVER(sunxi_dw_hdmi) = {
> -	.name	= "sunxi_dw_hdmi",
> -	.id	= UCLASS_DISPLAY,
> -	.ops	= &sunxi_dw_hdmi_ops,
> -	.probe	= sunxi_dw_hdmi_probe,
> -	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
> +static const struct udevice_id sunxi_dw_hdmi_ids[] = {
> +	{ .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
> +	{ }
>  };
>  
> -U_BOOT_DRVINFO(sunxi_dw_hdmi) = {
> -	.name = "sunxi_dw_hdmi"
> +U_BOOT_DRIVER(sunxi_dw_hdmi) = {
> +	.name		= "sunxi_dw_hdmi",
> +	.id		= UCLASS_DISPLAY,
> +	.of_match	= sunxi_dw_hdmi_ids,
> +	.probe		= sunxi_dw_hdmi_probe,
> +	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
> +	.ops		= &sunxi_dw_hdmi_ops,
>  };

Re: [PATCH 4/5] video: sunxi: dw-hdmi: Use DM for clock gates and resets

[Andre Przywara]

On Mon, 28 Nov 2022 01:02:27 -0600
Samuel Holland <samuel@sholland.org> wrote:

Hi,

> This abstracts away the CCU register layout, which is necessary for
> supporting new SoCs like H6 with a reorganized CCU. One of the resets is
> referenced from the PHY node instead of the controller node, so it will
> have to wait until the PHY code is factored out to a separate driver.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/video/sunxi/sunxi_dw_hdmi.c | 26 ++++++++++++++++++++------
>  1 file changed, 20 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
> index 4f5d0989286..04588b570fd 100644
> --- a/drivers/video/sunxi/sunxi_dw_hdmi.c
> +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
> @@ -5,12 +5,14 @@
>   * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
>   */
>  
> +#include <clk.h>
>  #include <common.h>
>  #include <display.h>
>  #include <dm.h>
>  #include <dw_hdmi.h>
>  #include <edid.h>
>  #include <log.h>
> +#include <reset.h>
>  #include <time.h>
>  #include <asm/io.h>
>  #include <asm/arch/clock.h>
> @@ -327,6 +329,8 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
>  	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
>  	struct sunxi_ccm_reg * const ccm =
>  		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> +	struct reset_ctl_bulk resets;
> +	struct clk_bulk clocks;
>  	int ret;
>  
>  	/* Set pll3 to 297 MHz */
> @@ -336,14 +340,24 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
>  	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
>  			CCM_HDMI_CTRL_PLL3);
>  
> -	/* Set ahb gating to pass */
> -	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
> +	/* This reset is referenced from the PHY devicetree node. */
>  	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
> -	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
> -	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
>  
> -	/* Clock on */
> -	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
> +	ret = reset_get_bulk(dev, &resets);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_get_bulk(dev, &clocks);
> +	if (ret)
> +		return ret;

I understand that it complicates thing a bit, for little benefit, but
shouldn't those two get operations be done in of_to_plat()?

Cheers,
Andre

> +
> +	ret = reset_deassert_bulk(&resets);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_enable_bulk(&clocks);
> +	if (ret)
> +		return ret;
>  
>  	sunxi_dw_hdmi_phy_init(&priv->hdmi);
>  

Re: [PATCH 3/5] video: sunxi: dw-hdmi: Read address from DT node

[Andre Przywara]

On Mon, 28 Nov 2022 01:02:26 -0600
Samuel Holland <samuel@sholland.org> wrote:

Hi,

> From: Jernej Skrabec <jernej.skrabec@gmail.com>
> 
> Currently HDMI controller MMIO address is hardcoded. Change that so
> address is read from DT node. That will make adding support for new
> variants a bit easier.

Looks good:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/video/sunxi/sunxi_dw_hdmi.c | 39 ++++++++++++++++++-----------
>  1 file changed, 24 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
> index e7265af7d8f..4f5d0989286 100644
> --- a/drivers/video/sunxi/sunxi_dw_hdmi.c
> +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
> @@ -56,10 +56,10 @@ static int sunxi_dw_hdmi_get_divider(uint clock)
>  		return 1;
>  }
>  
> -static void sunxi_dw_hdmi_phy_init(void)
> +static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
>  {
>  	struct sunxi_hdmi_phy * const phy =
> -		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
> +		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
>  	unsigned long tmo;
>  	u32 tmp;
>  
> @@ -113,10 +113,10 @@ static void sunxi_dw_hdmi_phy_init(void)
>  	writel(0x42494E47, &phy->unscramble);
>  }
>  
> -static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
> +static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
>  {
>  	struct sunxi_hdmi_phy * const phy =
> -		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
> +		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
>  	int div = sunxi_dw_hdmi_get_divider(clock);
>  	u32 tmp;
>  
> @@ -270,7 +270,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
>  	int phy_div;
>  
>  	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
> -	sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
> +	sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
>  
>  	return 0;
>  }
> @@ -291,10 +291,10 @@ static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
>  static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
>  				const struct display_timing *edid)
>  {
> +	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
>  	struct sunxi_hdmi_phy * const phy =
> -		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
> +		(struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
>  	struct display_plat *uc_plat = dev_get_uclass_plat(dev);
> -	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
>  	int ret;
>  
>  	ret = dw_hdmi_enable(&priv->hdmi, edid);
> @@ -316,7 +316,7 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
>  	 * again or othwerwise BSP driver won't work. Dummy read is
>  	 * needed or otherwise last write doesn't get written correctly.
>  	 */
> -	(void)readb(SUNXI_HDMI_BASE);
> +	(void)readb(priv->hdmi.ioaddr);
>  	writel(0, &phy->unscramble);
>  
>  	return 0;
> @@ -345,13 +345,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
>  	/* Clock on */
>  	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
>  
> -	sunxi_dw_hdmi_phy_init();
> -
> -	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
> -	priv->hdmi.i2c_clk_high = 0xd8;
> -	priv->hdmi.i2c_clk_low = 0xfe;
> -	priv->hdmi.reg_io_width = 1;
> -	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
> +	sunxi_dw_hdmi_phy_init(&priv->hdmi);
>  
>  	ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
>  	if (ret < 0) {
> @@ -364,6 +358,20 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
>  	return 0;
>  }
>  
> +static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
> +{
> +	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
> +	struct dw_hdmi *hdmi = &priv->hdmi;
> +
> +	hdmi->ioaddr = (ulong)dev_read_addr(dev);
> +	hdmi->i2c_clk_high = 0xd8;
> +	hdmi->i2c_clk_low = 0xfe;
> +	hdmi->reg_io_width = 1;
> +	hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
> +
> +	return 0;
> +}
> +
>  static const struct dm_display_ops sunxi_dw_hdmi_ops = {
>  	.read_edid = sunxi_dw_hdmi_read_edid,
>  	.enable = sunxi_dw_hdmi_enable,
> @@ -380,6 +388,7 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = {
>  	.id		= UCLASS_DISPLAY,
>  	.of_match	= sunxi_dw_hdmi_ids,
>  	.probe		= sunxi_dw_hdmi_probe,
> +	.of_to_plat	= sunxi_dw_hdmi_of_to_plat,
>  	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
>  	.ops		= &sunxi_dw_hdmi_ops,
>  };

Re: [PATCH 5/5] video: sunxi: dw-hdmi: Use DM for HVCC regulator

[Andre Przywara]

On Mon, 28 Nov 2022 01:02:28 -0600
Samuel Holland <samuel@sholland.org> wrote:

Hi,

> The HDMI PHY depends on the HVCC supply being enabled. So far we have
> relied on it being enabled by an earlier firmware stage (SPL or TF-A).
> Attempt to enable the regulator here, so we can remove that dependency.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  drivers/video/sunxi/sunxi_dw_hdmi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
> index 04588b570fd..963689358a6 100644
> --- a/drivers/video/sunxi/sunxi_dw_hdmi.c
> +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
> @@ -19,6 +19,7 @@
>  #include <asm/arch/lcdc.h>
>  #include <linux/bitops.h>
>  #include <linux/delay.h>
> +#include <power/regulator.h>
>  
>  struct sunxi_dw_hdmi_priv {
>  	struct dw_hdmi hdmi;
> @@ -331,8 +332,13 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
>  		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>  	struct reset_ctl_bulk resets;
>  	struct clk_bulk clocks;
> +	struct udevice *hvcc;
>  	int ret;
>  
> +	ret = device_get_supply_regulator(dev, "hvcc-supply", &hvcc);

Same as in the previous patch, I think this belongs into of_to_plat().

Cheers,
Andre

> +	if (!ret)
> +		regulator_set_enable(hvcc, true);
> +
>  	/* Set pll3 to 297 MHz */
>  	clock_set_pll3(297000000);
>