From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6745EC25B4E for ; Mon, 23 Jan 2023 01:11:32 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8E77E855A8; Mon, 23 Jan 2023 02:11:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7F87181F28; Mon, 23 Jan 2023 02:11:29 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id EF21381F28 for ; Mon, 23 Jan 2023 02:11:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6142AD7; Sun, 22 Jan 2023 17:12:07 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BCA7F3F5A1; Sun, 22 Jan 2023 17:11:24 -0800 (PST) Date: Mon, 23 Jan 2023 01:09:33 +0000 From: Andre Przywara To: Samuel Holland Cc: Jernej Skrabec , Anatolij Gustschin , Jagan Teki , Lukasz Majewski , Sean Anderson , u-boot@lists.denx.de Subject: Re: [PATCH 3/5] video: sunxi: dw-hdmi: Read address from DT node Message-ID: <20230123010933.019edcab@slackpad.lan> In-Reply-To: <20221128070229.4394-4-samuel@sholland.org> References: <20221128070229.4394-1-samuel@sholland.org> <20221128070229.4394-4-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Mon, 28 Nov 2022 01:02:26 -0600 Samuel Holland wrote: Hi, > From: Jernej Skrabec > > Currently HDMI controller MMIO address is hardcoded. Change that so > address is read from DT node. That will make adding support for new > variants a bit easier. Looks good: Reviewed-by: Andre Przywara Cheers, Andre > Signed-off-by: Jernej Skrabec > Signed-off-by: Samuel Holland > --- > > drivers/video/sunxi/sunxi_dw_hdmi.c | 39 ++++++++++++++++++----------- > 1 file changed, 24 insertions(+), 15 deletions(-) > > diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c > index e7265af7d8f..4f5d0989286 100644 > --- a/drivers/video/sunxi/sunxi_dw_hdmi.c > +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c > @@ -56,10 +56,10 @@ static int sunxi_dw_hdmi_get_divider(uint clock) > return 1; > } > > -static void sunxi_dw_hdmi_phy_init(void) > +static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi) > { > struct sunxi_hdmi_phy * const phy = > - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); > + (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); > unsigned long tmo; > u32 tmp; > > @@ -113,10 +113,10 @@ static void sunxi_dw_hdmi_phy_init(void) > writel(0x42494E47, &phy->unscramble); > } > > -static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div) > +static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div) > { > struct sunxi_hdmi_phy * const phy = > - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); > + (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); > int div = sunxi_dw_hdmi_get_divider(clock); > u32 tmp; > > @@ -270,7 +270,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) > int phy_div; > > sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div); > - sunxi_dw_hdmi_phy_set(mpixelclock, phy_div); > + sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div); > > return 0; > } > @@ -291,10 +291,10 @@ static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev, > static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, > const struct display_timing *edid) > { > + struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); > struct sunxi_hdmi_phy * const phy = > - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); > + (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS); > struct display_plat *uc_plat = dev_get_uclass_plat(dev); > - struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); > int ret; > > ret = dw_hdmi_enable(&priv->hdmi, edid); > @@ -316,7 +316,7 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, > * again or othwerwise BSP driver won't work. Dummy read is > * needed or otherwise last write doesn't get written correctly. > */ > - (void)readb(SUNXI_HDMI_BASE); > + (void)readb(priv->hdmi.ioaddr); > writel(0, &phy->unscramble); > > return 0; > @@ -345,13 +345,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) > /* Clock on */ > setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); > > - sunxi_dw_hdmi_phy_init(); > - > - priv->hdmi.ioaddr = SUNXI_HDMI_BASE; > - priv->hdmi.i2c_clk_high = 0xd8; > - priv->hdmi.i2c_clk_low = 0xfe; > - priv->hdmi.reg_io_width = 1; > - priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; > + sunxi_dw_hdmi_phy_init(&priv->hdmi); > > ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); > if (ret < 0) { > @@ -364,6 +358,20 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) > return 0; > } > > +static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) > +{ > + struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); > + struct dw_hdmi *hdmi = &priv->hdmi; > + > + hdmi->ioaddr = (ulong)dev_read_addr(dev); > + hdmi->i2c_clk_high = 0xd8; > + hdmi->i2c_clk_low = 0xfe; > + hdmi->reg_io_width = 1; > + hdmi->phy_set = sunxi_dw_hdmi_phy_cfg; > + > + return 0; > +} > + > static const struct dm_display_ops sunxi_dw_hdmi_ops = { > .read_edid = sunxi_dw_hdmi_read_edid, > .enable = sunxi_dw_hdmi_enable, > @@ -380,6 +388,7 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = { > .id = UCLASS_DISPLAY, > .of_match = sunxi_dw_hdmi_ids, > .probe = sunxi_dw_hdmi_probe, > + .of_to_plat = sunxi_dw_hdmi_of_to_plat, > .priv_auto = sizeof(struct sunxi_dw_hdmi_priv), > .ops = &sunxi_dw_hdmi_ops, > };