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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>, Fabio Estevam <festevam@denx.de>,
	Peng Fan <peng.fan@nxp.com>, Stefano Babic <sbabic@denx.de>,
	Ye Li <ye.li@nxp.com>
Subject: [PATCH] ddr: imx: Handle both 3733 and 3732 MTps rates
Date: Mon, 23 Jan 2023 17:53:19 +0100	[thread overview]
Message-ID: <20230123165319.15657-1-marex@denx.de> (raw)

The DDR calibration tool for i.MX8M currently produces 3732 MTps rate in
lpddr4_timing.c , while the PHY code expects 3733 MTps rate. Support both
variants to avoid surprises where the system fails to boot.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
---
 drivers/ddr/imx/phy/ddrphy_utils.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index b852c870f90..6a8b6be42b2 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -112,6 +112,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
 		dram_disable_bypass();
 		break;
 	case 3733:
+	case 3732:
 		dram_pll_init(MHZ(933));
 		dram_disable_bypass();
 		break;
-- 
2.39.0


             reply	other threads:[~2023-01-23 16:53 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-23 16:53 Marek Vasut [this message]
2023-01-30 22:08 ` [PATCH] ddr: imx: Handle both 3733 and 3732 MTps rates sbabic

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