From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A854C61DA4 for ; Fri, 10 Feb 2023 01:41:23 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 528AF85F67; Fri, 10 Feb 2023 02:41:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 6A21E85F67; Fri, 10 Feb 2023 02:41:19 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id B9C2D85857 for ; Fri, 10 Feb 2023 02:41:13 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 99CB14B3; Thu, 9 Feb 2023 17:41:55 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7424E3F71E; Thu, 9 Feb 2023 17:41:11 -0800 (PST) Date: Fri, 27 Jan 2023 22:59:16 +0000 From: Andre Przywara To: Samuel Holland Cc: Jagan Teki , Michael Trimarchi , Dario Binacchi , Hans de Goede , Lukasz Majewski , Sean Anderson , Simon Glass , u-boot@lists.denx.de Subject: Re: [PATCH v2 1/6] clk: sunxi: Add NAND clocks and resets Message-ID: <20230127225916.1fe4bc5a@slackpad.lan> In-Reply-To: <20230122220637.41496-2-samuel@sholland.org> References: <20230122220637.41496-1-samuel@sholland.org> <20230122220637.41496-2-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Sun, 22 Jan 2023 16:06:31 -0600 Samuel Holland wrote: > Currently NAND clock setup is done in board code, both in SPL and in > U-Boot proper. Add the NAND clocks/resets here so they can be used by > the "full" NAND driver once it is converted to the driver model. > > The bit locations are copied from the Linux CCU drivers. > > Reviewed-by: Jagan Teki > Signed-off-by: Samuel Holland Thanks for the changes, looks good now. Reviewed-by: Andre Przywara Cheers, Andre > --- > > Changes in v2: > - Fix A80 bus clock/reset bit positions > > drivers/clk/sunxi/clk_a10.c | 2 ++ > drivers/clk/sunxi/clk_a10s.c | 2 ++ > drivers/clk/sunxi/clk_a23.c | 3 +++ > drivers/clk/sunxi/clk_a31.c | 6 ++++++ > drivers/clk/sunxi/clk_a64.c | 3 +++ > drivers/clk/sunxi/clk_a80.c | 8 ++++++++ > drivers/clk/sunxi/clk_a83t.c | 3 +++ > drivers/clk/sunxi/clk_h3.c | 3 +++ > drivers/clk/sunxi/clk_h6.c | 6 ++++++ > drivers/clk/sunxi/clk_h616.c | 6 ++++++ > drivers/clk/sunxi/clk_r40.c | 3 +++ > 11 files changed, 45 insertions(+) > > diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c > index abd4e8b738..f27306fe33 100644 > --- a/drivers/clk/sunxi/clk_a10.c > +++ b/drivers/clk/sunxi/clk_a10.c > @@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] = { > [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), > [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), > [CLK_AHB_MMC3] = GATE(0x060, BIT(11)), > + [CLK_AHB_NAND] = GATE(0x060, BIT(13)), > [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), > [CLK_AHB_SPI0] = GATE(0x060, BIT(20)), > [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), > @@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] = { > [CLK_APB1_UART6] = GATE(0x06c, BIT(22)), > [CLK_APB1_UART7] = GATE(0x06c, BIT(23)), > > + [CLK_NAND] = GATE(0x080, BIT(31)), > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > [CLK_SPI2] = GATE(0x0a8, BIT(31)), > diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c > index e486cedd48..16ac589bb2 100644 > --- a/drivers/clk/sunxi/clk_a10s.c > +++ b/drivers/clk/sunxi/clk_a10s.c > @@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[] = { > [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), > [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), > [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), > + [CLK_AHB_NAND] = GATE(0x060, BIT(13)), > [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), > [CLK_AHB_SPI0] = GATE(0x060, BIT(20)), > [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), > @@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[] = { > [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), > [CLK_APB1_UART3] = GATE(0x06c, BIT(19)), > > + [CLK_NAND] = GATE(0x080, BIT(31)), > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > [CLK_SPI2] = GATE(0x0a8, BIT(31)), > diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c > index d94fecadd5..45d5ba75bf 100644 > --- a/drivers/clk/sunxi/clk_a23.c > +++ b/drivers/clk/sunxi/clk_a23.c > @@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] = { > [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), > [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), > [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), > + [CLK_BUS_NAND] = GATE(0x060, BIT(13)), > [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), > [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), > [CLK_BUS_OTG] = GATE(0x060, BIT(24)), > @@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] = { > [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), > [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), > > + [CLK_NAND] = GATE(0x080, BIT(31)), > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > > @@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = { > [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), > [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), > [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), > + [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), > [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), > [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), > [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), > diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c > index 360658912d..6ca800050e 100644 > --- a/drivers/clk/sunxi/clk_a31.c > +++ b/drivers/clk/sunxi/clk_a31.c > @@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] = { > [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), > [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), > [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), > + [CLK_AHB1_NAND1] = GATE(0x060, BIT(12)), > + [CLK_AHB1_NAND0] = GATE(0x060, BIT(13)), > [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)), > [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)), > [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)), > @@ -43,6 +45,8 @@ static struct ccu_clk_gate a31_gates[] = { > [CLK_APB2_UART4] = GATE(0x06c, BIT(20)), > [CLK_APB2_UART5] = GATE(0x06c, BIT(21)), > > + [CLK_NAND0] = GATE(0x080, BIT(31)), > + [CLK_NAND1] = GATE(0x084, BIT(31)), > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > [CLK_SPI2] = GATE(0x0a8, BIT(31)), > @@ -65,6 +69,8 @@ static struct ccu_reset a31_resets[] = { > [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), > [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), > [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), > + [RST_AHB1_NAND1] = RESET(0x2c0, BIT(12)), > + [RST_AHB1_NAND0] = RESET(0x2c0, BIT(13)), > [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)), > [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)), > [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)), > diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c > index 8c81b1ac45..4a4a19b478 100644 > --- a/drivers/clk/sunxi/clk_a64.c > +++ b/drivers/clk/sunxi/clk_a64.c > @@ -19,6 +19,7 @@ static const struct ccu_clk_gate a64_gates[] = { > [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), > [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), > [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), > + [CLK_BUS_NAND] = GATE(0x060, BIT(13)), > [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), > [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), > [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), > @@ -39,6 +40,7 @@ static const struct ccu_clk_gate a64_gates[] = { > [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), > [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), > > + [CLK_NAND] = GATE(0x080, BIT(31)), > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > > @@ -58,6 +60,7 @@ static const struct ccu_reset a64_resets[] = { > [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), > [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), > [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), > + [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), > [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), > [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), > [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), > diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c > index 3c9eb14316..c5834f4410 100644 > --- a/drivers/clk/sunxi/clk_a80.c > +++ b/drivers/clk/sunxi/clk_a80.c > @@ -14,12 +14,18 @@ > #include > > static const struct ccu_clk_gate a80_gates[] = { > + [CLK_NAND0_0] = GATE(0x400, BIT(31)), > + [CLK_NAND0_1] = GATE(0x404, BIT(31)), > + [CLK_NAND1_0] = GATE(0x408, BIT(31)), > + [CLK_NAND1_1] = GATE(0x40c, BIT(31)), > [CLK_SPI0] = GATE(0x430, BIT(31)), > [CLK_SPI1] = GATE(0x434, BIT(31)), > [CLK_SPI2] = GATE(0x438, BIT(31)), > [CLK_SPI3] = GATE(0x43c, BIT(31)), > > [CLK_BUS_MMC] = GATE(0x580, BIT(8)), > + [CLK_BUS_NAND0] = GATE(0x580, BIT(13)), > + [CLK_BUS_NAND1] = GATE(0x580, BIT(12)), > [CLK_BUS_SPI0] = GATE(0x580, BIT(20)), > [CLK_BUS_SPI1] = GATE(0x580, BIT(21)), > [CLK_BUS_SPI2] = GATE(0x580, BIT(22)), > @@ -42,6 +48,8 @@ static const struct ccu_clk_gate a80_gates[] = { > > static const struct ccu_reset a80_resets[] = { > [RST_BUS_MMC] = RESET(0x5a0, BIT(8)), > + [RST_BUS_NAND0] = RESET(0x5a0, BIT(13)), > + [RST_BUS_NAND1] = RESET(0x5a0, BIT(12)), > [RST_BUS_SPI0] = RESET(0x5a0, BIT(20)), > [RST_BUS_SPI1] = RESET(0x5a0, BIT(21)), > [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)), > diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c > index 3562da61d1..71be95be26 100644 > --- a/drivers/clk/sunxi/clk_a83t.c > +++ b/drivers/clk/sunxi/clk_a83t.c > @@ -17,6 +17,7 @@ static struct ccu_clk_gate a83t_gates[] = { > [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), > [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), > [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), > + [CLK_BUS_NAND] = GATE(0x060, BIT(13)), > [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), > [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), > [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), > @@ -36,6 +37,7 @@ static struct ccu_clk_gate a83t_gates[] = { > [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), > [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), > > + [CLK_NAND] = GATE(0x080, BIT(31)), > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > > @@ -54,6 +56,7 @@ static struct ccu_reset a83t_resets[] = { > [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), > [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), > [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), > + [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), > [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), > [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), > [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), > diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c > index 17ab3b5c27..25fe22c52a 100644 > --- a/drivers/clk/sunxi/clk_h3.c > +++ b/drivers/clk/sunxi/clk_h3.c > @@ -19,6 +19,7 @@ static struct ccu_clk_gate h3_gates[] = { > [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), > [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), > [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), > + [CLK_BUS_NAND] = GATE(0x060, BIT(13)), > [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), > [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), > [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), > @@ -44,6 +45,7 @@ static struct ccu_clk_gate h3_gates[] = { > > [CLK_BUS_EPHY] = GATE(0x070, BIT(0)), > > + [CLK_NAND] = GATE(0x080, BIT(31)), > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > > @@ -66,6 +68,7 @@ static struct ccu_reset h3_resets[] = { > [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), > [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), > [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), > + [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), > [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), > [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), > [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), > diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c > index 041bc5e80e..3e3a21cda8 100644 > --- a/drivers/clk/sunxi/clk_h6.c > +++ b/drivers/clk/sunxi/clk_h6.c > @@ -18,6 +18,10 @@ static struct ccu_clk_gate h6_gates[] = { > > [CLK_APB1] = GATE_DUMMY, > > + [CLK_NAND0] = GATE(0x810, BIT(31)), > + [CLK_NAND1] = GATE(0x814, BIT(31)), > + [CLK_BUS_NAND] = GATE(0x82c, BIT(0)), > + > [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), > [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), > [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), > @@ -58,6 +62,8 @@ static struct ccu_clk_gate h6_gates[] = { > }; > > static struct ccu_reset h6_resets[] = { > + [RST_BUS_NAND] = RESET(0x82c, BIT(16)), > + > [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), > [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), > [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c > index 964636d728..7d8b04263a 100644 > --- a/drivers/clk/sunxi/clk_h616.c > +++ b/drivers/clk/sunxi/clk_h616.c > @@ -17,6 +17,10 @@ static struct ccu_clk_gate h616_gates[] = { > > [CLK_APB1] = GATE_DUMMY, > > + [CLK_NAND0] = GATE(0x810, BIT(31)), > + [CLK_NAND1] = GATE(0x814, BIT(31)), > + [CLK_BUS_NAND] = GATE(0x82c, BIT(0)), > + > [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), > [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), > [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), > @@ -67,6 +71,8 @@ static struct ccu_clk_gate h616_gates[] = { > }; > > static struct ccu_reset h616_resets[] = { > + [RST_BUS_NAND] = RESET(0x82c, BIT(16)), > + > [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), > [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), > [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c > index ef743d65b7..7bc49f617e 100644 > --- a/drivers/clk/sunxi/clk_r40.c > +++ b/drivers/clk/sunxi/clk_r40.c > @@ -18,6 +18,7 @@ static struct ccu_clk_gate r40_gates[] = { > [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), > [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), > [CLK_BUS_MMC3] = GATE(0x060, BIT(11)), > + [CLK_BUS_NAND] = GATE(0x060, BIT(13)), > [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), > [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), > [CLK_BUS_SPI2] = GATE(0x060, BIT(22)), > @@ -48,6 +49,7 @@ static struct ccu_clk_gate r40_gates[] = { > [CLK_BUS_UART6] = GATE(0x06c, BIT(22)), > [CLK_BUS_UART7] = GATE(0x06c, BIT(23)), > > + [CLK_NAND] = GATE(0x080, BIT(31)), > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > [CLK_SPI2] = GATE(0x0a8, BIT(31)), > @@ -70,6 +72,7 @@ static struct ccu_reset r40_resets[] = { > [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), > [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), > [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), > + [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), > [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), > [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), > [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),