[PATCH 09/10] arm: imx: imx8m: Program CSU and TZASC if PSCI provider

Marek Vasut
2022-12-22T00:48:41Z

In case U-Boot is the PSCI provider, it is necessary to correctly
program CSU and TZASC registers. Those are poorly documented, so
push in the correct values.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
arch/arm/mach-imx/imx8m/soc.c | 25 ++++++++++++++++++++++
2 files changed, 26 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 3034d280cc3..1559bf6d218 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -31,6 +31,7 @@
#define CCM_BASE_ADDR 0x30380000
#define SRC_BASE_ADDR 0x30390000
#define GPC_BASE_ADDR 0x303A0000
+#define CSU_BASE_ADDR 0x303E0000

#define SYSCNT_RD_BASE_ADDR 0x306A0000
#define SYSCNT_CMP_BASE_ADDR 0x306B0000
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 706ba8509da..99c41c654a1 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -561,6 +561,29 @@ static void imx8m_setup_snvs(void)
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}

+static void imx8m_setup_csu_tzasc(void)
+{
+ const uintptr_t tzasc_base[4] = {
+ 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
+ };
+ int i, j;
+
+ if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
+ return;
+
+ /* CSU */
+ for (i = 0; i < 64; i++)
+ writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
+
+ /* TZASC */
+ for (j = 0; j < 4; j++) {
+ writel(0x77777777, (void *)(tzasc_base[j]));
+ writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
+ for (i = 0; i <= 0x10; i += 4)
+ writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
+ }
+}
+
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -613,6 +636,8 @@ int arch_cpu_init(void)

imx8m_setup_snvs();

+ imx8m_setup_csu_tzasc();
+
return 0;
}

--
2.35.1