From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5992DC05027 for ; Thu, 2 Feb 2023 01:59:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AC73385E80; Thu, 2 Feb 2023 02:59:09 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eiZH+5my"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BB5C785E2B; Thu, 2 Feb 2023 02:59:04 +0100 (CET) Received: from mail-il1-x132.google.com (mail-il1-x132.google.com [IPv6:2607:f8b0:4864:20::132]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B7BAB85E7B for ; Thu, 2 Feb 2023 02:58:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=aford173@gmail.com Received: by mail-il1-x132.google.com with SMTP id l15so248714ilj.5 for ; Wed, 01 Feb 2023 17:58:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SlL/wXYNoj2R90lW162lSbT4TAJEy7MLEDiqPWbjVi4=; b=eiZH+5myOo0NBAMqF/keslAX5pTL8fBxcTmecPybDZh0WfObmoXMDfXudgMUNxY0H0 kt/vf0ZbTQrm6VQ73n1N0bxg+i1BO77QNJ52L4dSABistTmUavse674aabwhUGela59E E8kQfQad7ojVi/obMpF+Z8HODRpHPLfupkHoNRtXppvo9ofVY1sBpWaGdjHpZrhfdRzD EQszgvDc+iw+4EHLtuiYdJXlVwinHHqLkFjbXxDK7ljObVvqyYT8yytdDi+TAyltcf7p Jl4prOhaEY3aKkhnlnLDfYH4z3uG56UcyERC06SuS5Wv61LZZpj6xgp4fS3JPq/gC4P5 p3Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SlL/wXYNoj2R90lW162lSbT4TAJEy7MLEDiqPWbjVi4=; b=vDROAegrr+03cgb0V4SPHjMU+oOIY75tD4qi4KiyTepD1hbyYSd2kVH05HLYnY2TZE AZa8hzM2QAS3MLMdISO5zFtgFXoTteYSQON4qdvayJJOHEUX9p1XcV4nDT/tCqmOXGbD 5Q/Gc+XsFn+B9yX+1vcK6jV8Rd9Ffri6BYKKYER3aP8YP9+TFdrF6s6WSi0x1SUcri5E Epg+O2DotjXGN3Df3jr6iRqf4lVcBgp69ovMphNgdOBlZRDziZwZyCRNrMySex+ieK/6 ZPV4bxd7U167NI2jcUA1YLcpCo6d7hcYvAVdmiBAFKvY1ZLCPs2KzZWxYZMXf2l43gsv cdog== X-Gm-Message-State: AO0yUKXWULSWkkfYHILGvQoaFGIJdj0KT57S/mX0v3hx3LWWtOh9gOPT Hh4k2pPTycS/UR5gDs1S9TO5bbGYAMY= X-Google-Smtp-Source: AK7set89qgdVQZiZeOVmTr9OnQIa+cSV3x1dIljPDKUN5UxCXgWip9UwACYSifwGv/Vy6O0MdI8j2g== X-Received: by 2002:a05:6e02:152b:b0:310:a3c6:f429 with SMTP id i11-20020a056e02152b00b00310a3c6f429mr3737495ilu.9.1675303136716; Wed, 01 Feb 2023 17:58:56 -0800 (PST) Received: from aford-IdeaCentre-A730.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id t190-20020a0254c7000000b0038a3b8aaf11sm7162439jaa.37.2023.02.01.17.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 17:58:55 -0800 (PST) From: Adam Ford To: u-boot@lists.denx.de Cc: sbabic@denx.de, aford@beaconembedded.com, Adam Ford Subject: [PATCH V2 2/2] configs: imx: imx8mm_beacon: Add config option for QSPI booting Date: Wed, 1 Feb 2023 19:58:41 -0600 Message-Id: <20230202015841.248835-2-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202015841.248835-1-aford173@gmail.com> References: <20230202015841.248835-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean The imx8mm_beacon SOM has a QSPI part attached to the FSPI controller. Update the header and spl files to support booting from NOR flash and add imx8mm_beacon_fspi_defconfig to support this configuration. Signed-off-by: Adam Ford --- V2: Rebase and rename CONFIG_SYS_UBOOT_BASE to CFG_SYS_UBOOT_BASE diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index a5f337aa17..b2830c5223 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -36,6 +36,8 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) return BOOT_DEVICE_MMC2; case USB_BOOT: return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; default: return BOOT_DEVICE_NONE; } @@ -46,6 +48,11 @@ static void spl_dram_init(void) ddr_init(&dram_timing); } +void spl_board_init(void) +{ + arch_misc_init(); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig new file mode 100644 index 0000000000..805fd3f671 --- /dev/null +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -0,0 +1,155 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" +CONFIG_SPL_TEXT_BASE=0x7E2000 +CONFIG_TARGET_IMX8MM_BEACON=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_LTO=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;" +CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x920000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_CRC32=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_POWER=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x800000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="FEC" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_SPL_PHY=y +CONFIG_SPL_NOP_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y +CONFIG_FSPI_CONF_HEADER=y +CONFIG_FSPI_CONF_FILE="fspi_header.bin" diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index d85ae21e23..6d70957e5e 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,8 +9,17 @@ #include #include +#define UBOOT_ITB_OFFSET 0x57C00 +#define FSPI_CONF_BLOCK_SIZE 0x1000 +#define UBOOT_ITB_OFFSET_FSPI \ + (UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE) +#ifdef CONFIG_FSPI_CONF_HEADER +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI) +#else #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#endif #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -- 2.34.1