[PATCH v2 00/10] cache operation cleanups for Andes AE350 platform

Yu Chien Peter Lin
2023-02-06T08:11:13Z

This patchset is intended to enable L2-cache in U-boot SPL, along with
cache operations cleanup for AE350 platforms.

Changes v1 -> v2:
- Drop plicsw related patch
- Include RB tags from Rick and Leo

The patchset is based on commit:
a209c3e6b48cf042d0220245a2d1636f74389c17

Leo Yu-Chi Liang (1):
riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

Yu Chien Peter Lin (9):
board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2
platform
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
riscv: ae350: dts: Update L2 cache compatible string
riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
configs: ae350: Increase maximum retry count for AE350 platforms
configs: ae350: Display CPU and board info for AE350 platforms
driver: cache-v5l2: Fix type casting warning on RV32

arch/riscv/cpu/ax25/Kconfig | 11 +--
arch/riscv/cpu/ax25/cache.c | 118 ++++++++----------------
arch/riscv/cpu/ax25/cpu.c | 49 +++-------
arch/riscv/dts/ae350_32.dts | 2 +-
arch/riscv/dts/ae350_64.dts | 2 +-
arch/riscv/include/asm/arch-andes/csr.h | 29 ++++++
board/AndesTech/ax25-ae350/ax25-ae350.c | 17 ++--
configs/ae350_rv32_defconfig | 3 +
configs/ae350_rv32_spl_defconfig | 5 +
configs/ae350_rv32_spl_xip_defconfig | 5 +
configs/ae350_rv32_xip_defconfig | 3 +
configs/ae350_rv64_defconfig | 3 +
configs/ae350_rv64_spl_defconfig | 5 +
configs/ae350_rv64_spl_xip_defconfig | 5 +
configs/ae350_rv64_xip_defconfig | 3 +
drivers/cache/Kconfig | 1 -
drivers/cache/cache-v5l2.c | 36 ++++++--
17 files changed, 149 insertions(+), 148 deletions(-)
create mode 100644 arch/riscv/include/asm/arch-andes/csr.h

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2.34.1