[PATCH v2 04/10] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

Yu Chien Peter Lin
2023-02-06T08:12:23Z

As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.

[0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/cpu/ax25/cpu.c | 49 ++++++-------------------
arch/riscv/include/asm/arch-andes/csr.h | 29 +++++++++++++++
2 files changed, 41 insertions(+), 37 deletions(-)
create mode 100644 arch/riscv/include/asm/arch-andes/csr.h

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index a46674f7c2..2c7565ad49 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Andes Technology Corporation
+ * Copyright (C) 2023 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/

@@ -10,23 +10,7 @@
#include <irq_func.h>
#include <asm/cache.h>
#include <asm/csr.h>
-
-#define CSR_MCACHE_CTL 0x7ca
-#define CSR_MMISC_CTL 0x7d0
-#define CSR_MARCHID 0xf12
-
-#define V5_MCACHE_CTL_IC_EN_OFFSET 0
-#define V5_MCACHE_CTL_DC_EN_OFFSET 1
-#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
-#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
-#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
-
-#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
-
+#include <asm/arch-andes/csr.h>

/*
* cleanup_before_linux() is called just before we call linux
@@ -38,38 +22,29 @@ int cleanup_before_linux(void)
{
disable_interrupts();

- /* turn off I/D-cache */
cache_flush();
- icache_disable();
- dcache_disable();

return 0;
}

void harts_early_init(void)
{
+ /* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
- unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+
+ mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
+ MCACHE_CTL_DC_EN);

- if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
- mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
- if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
- mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
- if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
- mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
- if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
- mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);

/*
- * Check DC_COHEN_EN, if cannot write to mcache_ctl,
- * we assume this bitmap not support L2 CM
+ * Check mcache_ctl.DC_COHEN, we assume this platform does
+ * not support CM if the bit is hard-wired to 0.
*/
- mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
- if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
- /* Wait for DC_COHSTA bit be set */
- while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
- mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
+ /* Wait for DC_COHSTA bit to be set */
+ while (!(csr_read(CSR_MCACHE_CTL)& MCACHE_CTL_DC_COHSTA));
}
}
}
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
new file mode 100644
index 0000000000..a03ccd5b3e
--- /dev/null
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+
+#ifndef _ASM_ANDES_CSR_H
+#define _ASM_ANDES_CSR_H
+
+#include <asm/asm.h>
+#include <linux/const.h>
+
+#define CSR_MCACHE_CTL 0x7ca
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MARCHID 0xf12
+#define CSR_MCCTLCOMMAND 0x7cc
+
+#define MCACHE_CTL_IC_EN_OFFSET 0
+#define MCACHE_CTL_DC_EN_OFFSET 1
+#define MCACHE_CTL_DC_COHEN_OFFSET 19
+#define MCACHE_CTL_DC_COHSTA_OFFSET 20
+
+#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
+#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
+#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
+#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
+
+#define CCTL_L1D_WBINVAL_ALL 6
+
+#endif /* _ASM_ANDES_CSR_H */
--
2.34.1