From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35FD2C636D3 for ; Thu, 9 Feb 2023 21:53:38 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4D9B485F72; Thu, 9 Feb 2023 22:53:32 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1675979613; bh=sEU7rUIYG8fc6qzWjwYCeXkXbSq3nq+/zDSY8wZCWLI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=jSfABsuMYBISiOAyE3NZC3NBuDGMaPcJpR7y2S+D22z6Oe0hUXKROsRZ/GN1koekr ZkxexYRBTPsVnqr2+dTyVrCtApK/E53iM3NRreISPKCghy7/fqpz/qzaHcSwSh+XF7 S8qkKQnBIHIBWxCPfDHQx3qAGpYCzdNor6/M+otWLtQEck5Iw2Tp6wQ4LApyryvoAY bSl1HSpfEslFHUOEqngTnVKWISE6cRffvywv9cMIlFlRwlFaWvZy15XI8uhhiAFLMp dNjTQdJS9NMR0wesWRrMaKg8591iDJElYIjCo6pjeSiGT9UqY+dWM1fAJ/Z/e3K/4m 3Q6+8doPi2cgg== Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 1AF1585F63; Thu, 9 Feb 2023 22:51:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1675979496; bh=sEU7rUIYG8fc6qzWjwYCeXkXbSq3nq+/zDSY8wZCWLI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CH5/+kpktC0R+et7LZLqXD8My98v8sBL/vWIp7HlKJJCRWDnE35j8B/ziccgbw+MU hxMKVD1VH19imc4Jp6SCjzDGnSTug159yJHOhea67giJCsQa65T1u4DQP7y7iIPivQ Yi+bamgwqZpWOvbLso5q+0x+ncKxJDKLPY9vl/SeHvDZXvwoCXmfuqmAYhuA+EqGvO EJaTjDaEirG08Lbabt5S8uFbTf2LZnI/vVFgaKs+CF0HuLBt6ar03JRSrVTKetfCCI RQ2roKEQh82x193amCwF0bh1/5MDqRKGdsiuvs7qVe5eIo+ZHSNsdjl5zfC3X6CTYX nvLZunYt3/irg== From: Marek Vasut To: u-boot@lists.denx.de Cc: Marek Vasut , "Ariel D'Alessandro" , "NXP i.MX U-Boot Team" , Andrey Zhizhikin , Fabio Estevam , Joe Hershberger , Lukasz Majewski , Marcel Ziswiler , Michael Trimarchi , Peng Fan , Ramon Fried , Sean Anderson , Stefano Babic , Tim Harvey , Tommaso Merciai Subject: [PATCH v2 10/10] arm64: imx8mp: Drop EQoS GPR[1] board workaround Date: Thu, 9 Feb 2023 22:50:48 +0100 Message-Id: <20230209215048.259223-10-marex@denx.de> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209215048.259223-1-marex@denx.de> References: <20230209215048.259223-1-marex@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean The EQoS interface mode is now configured in common board_interface_eth_init() and called by EQoS MAC driver when appropriate. Drop the board side duplicates if the same functionality. Signed-off-by: Marek Vasut --- Cc: "Ariel D'Alessandro" Cc: "NXP i.MX U-Boot Team" Cc: Andrey Zhizhikin Cc: Fabio Estevam Cc: Joe Hershberger Cc: Lukasz Majewski Cc: Marcel Ziswiler Cc: Marek Vasut Cc: Michael Trimarchi Cc: Peng Fan Cc: Ramon Fried Cc: Sean Anderson Cc: Stefano Babic Cc: Tim Harvey Cc: Tommaso Merciai Cc: u-boot@lists.denx.de --- V2: Fix the advantech board build --- .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 17 +---------------- .../dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 14 -------------- board/engicam/imx8mp/icore_mx8mp.c | 16 ---------------- board/freescale/imx8mp_evk/imx8mp_evk.c | 17 ----------------- board/gateworks/venice/venice.c | 15 --------------- board/msc/sm2s_imx8mp/sm2s_imx8mp.c | 15 --------------- board/toradex/verdin-imx8mp/verdin-imx8mp.c | 16 ---------------- 7 files changed, 1 insertion(+), 109 deletions(-) diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index aa9687f7a9d..56068b0c01e 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -113,7 +113,7 @@ static const iomux_v3_cfg_t eqos_rst_pads[] = { MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static void setup_iomux_eqos(void) +static void setup_eqos(void) { imx_iomux_v3_setup_multiple_pads(eqos_rst_pads, ARRAY_SIZE(eqos_rst_pads)); @@ -124,21 +124,6 @@ static void setup_iomux_eqos(void) gpio_direction_output(EQOS_RST_PAD, 1); mdelay(100); } - -static int setup_eqos(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - setup_iomux_eqos(); - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&gpr->gpr[1], - IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); - setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); - - return set_clk_eqos(ENET_125MHZ); -} #endif /* CONFIG_DWC_ETH_QOS */ int board_phy_config(struct phy_device *phydev) diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 9d8e19d994a..cb9973900bd 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -37,19 +37,6 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -static void setup_eqos(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Set INTF as RGMII, enable RGMII TXC clock. */ - clrsetbits_le32(&gpr->gpr[1], - IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); - setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); - - set_clk_eqos(ENET_125MHZ); -} - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = @@ -127,7 +114,6 @@ int dh_setup_mac_address(void) int board_init(void) { - setup_eqos(); setup_fec(); return 0; } diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c index b309a12df08..b80513c7957 100644 --- a/board/engicam/imx8mp/icore_mx8mp.c +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -34,19 +34,6 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -static int setup_eqos(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&gpr->gpr[1], - IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); - setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); - - return set_clk_eqos(ENET_125MHZ); -} - #if CONFIG_IS_ENABLED(NET) int board_phy_config(struct phy_device *phydev) { @@ -61,9 +48,6 @@ int board_init(void) if (CONFIG_IS_ENABLED(FEC_MXC)) setup_fec(); - if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) - setup_eqos(); - return 0; } diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 8971a827df3..0fefdafadfa 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -29,19 +29,6 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -static int setup_eqos(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&gpr->gpr[1], - IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); - setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); - - return set_clk_eqos(ENET_125MHZ); -} - #if CONFIG_IS_ENABLED(NET) int board_phy_config(struct phy_device *phydev) { @@ -59,10 +46,6 @@ int board_init(void) setup_fec(); } - if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) { - ret = setup_eqos(); - } - return ret; } diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index c4d86c26a9b..bc8937b366c 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -58,19 +58,6 @@ static int setup_fec(void) return 0; } -static int setup_eqos(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&gpr->gpr[1], - IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); - setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); - - return set_clk_eqos(ENET_125MHZ); -} - int board_phy_config(struct phy_device *phydev) { unsigned short val; @@ -115,8 +102,6 @@ int board_init(void) if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec(); - if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) - setup_eqos(); return 0; } diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c index 3913c4f2427..6ccbf02db06 100644 --- a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c @@ -30,19 +30,6 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -static int setup_eqos(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&gpr->gpr[1], - IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); - setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); - - return set_clk_eqos(ENET_125MHZ); -} - int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) @@ -54,7 +41,5 @@ int board_init(void) { setup_fec(); - setup_eqos(); - return 0; } diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 9c2e44a1229..5490d3ed44a 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -49,19 +49,6 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -static int setup_eqos(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* set INTF as RGMII, enable RGMII TXC clock */ - clrsetbits_le32(&gpr->gpr[1], - IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); - setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); - - return set_clk_eqos(ENET_125MHZ); -} - #if IS_ENABLED(CONFIG_NET) int board_phy_config(struct phy_device *phydev) { @@ -78,9 +65,6 @@ int board_init(void) if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec(); - if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) - ret = setup_eqos(); - return ret; } -- 2.39.1