From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7262C61DA4 for ; Thu, 9 Feb 2023 21:55:37 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 213E785F7D; Thu, 9 Feb 2023 22:55:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1675979730; bh=llH2BmpF6XFAK2rpwwTdYS4oVNbTMDQmWNpxlkrjeIM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=oIzbnKxnxELNoecyuCti8x4JJfTvrIjc5KfHXcXPH2cdafhCXcE+gsP/VFsiF9dUX YuT2QIGdLfEb4qZwpZRaInx+1WVWc7nchKA0DQvJ3KV8tmg6zkrMN76os1zZKjWnmF 0MfM6JWs4L7ZfMfZbY4126Nn/kH+KyqIXDnr2NGSaT6GDzU5UnbLU9q6y5cFNkmj3R 6YvAYHJytIXwtuwG1SXZN/McTcLygt0eDazjlA485GWFBLS7bD6eANNIbziYw/UyRn OfF2vK7iMVs2d2mWfudx/cFqGYYQ1gurRvXdBGQydYGAYwMbA6hMfIBtV367uOYx5F jXf59ikhZbvhA== Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 88A8A85EB4; Thu, 9 Feb 2023 22:51:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1675979489; bh=llH2BmpF6XFAK2rpwwTdYS4oVNbTMDQmWNpxlkrjeIM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lWVemm/DJPX7oZ/BgaE8584djo3wwfUzIYlHFMQJkTL4JnxBKVLkrfdZenNae7BNK ohSuMZjbdqZMrFfmwAZBYUsDhgcvJU/f5fh00yLxc92SfRYClzfcd94ljp4oaO+ZgI 6OEa9C5noSc3MEig3tnyu+wetH5Ftt9ch272Ih6JhAF5ybuGoWeQoGNa9+CETtNOdh NigMh6nR+2gaRpnPu5177q/RJbU1/4wRlmAeLFRe+kB9RuD5GXs82Q8GZUZkTNd2kl HJash0kSeD1UCBrgI8YEtJey93a7BbfqAf5CvudQxGkTDmUmcn2hoUSHd0c20ZMDlv hCfb8X+1d1GQw== From: Marek Vasut To: u-boot@lists.denx.de Cc: Marek Vasut , Ramon Fried , "Ariel D'Alessandro" , "NXP i.MX U-Boot Team" , Andrey Zhizhikin , Fabio Estevam , Joe Hershberger , Lukasz Majewski , Marcel Ziswiler , Michael Trimarchi , Peng Fan , Sean Anderson , Stefano Babic , Tim Harvey , Tommaso Merciai Subject: [PATCH v2 08/10] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus Date: Thu, 9 Feb 2023 22:50:46 +0100 Message-Id: <20230209215048.259223-8-marex@denx.de> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209215048.259223-1-marex@denx.de> References: <20230209215048.259223-1-marex@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Implement common board_interface_eth_init() and call it from the DWMAC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Plus DWMAC and supersedes current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Reviewed-by: Ramon Fried Signed-off-by: Marek Vasut --- Cc: "Ariel D'Alessandro" Cc: "NXP i.MX U-Boot Team" Cc: Andrey Zhizhikin Cc: Fabio Estevam Cc: Joe Hershberger Cc: Lukasz Majewski Cc: Marcel Ziswiler Cc: Marek Vasut Cc: Michael Trimarchi Cc: Peng Fan Cc: Ramon Fried Cc: Sean Anderson Cc: Stefano Babic Cc: Tim Harvey Cc: Tommaso Merciai Cc: u-boot@lists.denx.de --- V2: - Add RB from Ramon - Handle RGMII_ID/RGMII_RXID/RGMII_TXID just like plain RGMII --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 8 ++++- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 40 ++++++++++++++++++++++ drivers/net/dwc_eth_qos_imx.c | 4 +++ 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 1559bf6d218..1818b459fa6 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -89,7 +89,13 @@ #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 -#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL BIT(20) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN BIT(19) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII (1 << 16) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16) #define FEC_QUIRK_ENET_MAC #ifdef CONFIG_ARMV8_PSCI /* Final jump location */ diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 494bfbedc8c..6d3539ec982 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -872,6 +873,45 @@ int set_clk_eqos(enum enet_freq type) return 0; } + +int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + clrbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN); + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + setbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII); + break; + case PHY_INTERFACE_MODE_RMII: + setbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + setbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII); + break; + default: + return -EINVAL; + } + + return 0; +} #endif #ifdef CONFIG_FEC_MXC diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index fb4e6d38e24..f565a5fd21a 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -55,6 +55,10 @@ static int eqos_probe_resources_imx(struct udevice *dev) return -EINVAL; } + ret = board_interface_eth_init(dev, interface); + if (ret) + return -EINVAL; + eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); -- 2.39.1