From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6EE9C636CC for ; Sat, 11 Feb 2023 10:08:01 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5F81985677; Sat, 11 Feb 2023 11:07:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=emagii.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=emagii.com header.i=@emagii.com header.b="uAYJGb5T"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 30CE18578A; Sat, 11 Feb 2023 11:07:56 +0100 (CET) Received: from emagii.se (www.emagii.com [185.133.207.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D4135856D3 for ; Sat, 11 Feb 2023 11:07:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=emagii.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot@emagii.com Received: from valinor.ownit.se (84-55-68-216.customers.ownit.se [84.55.68.216]) by emagii.se (Postfix) with ESMTPSA id E3ED7120189; Sat, 11 Feb 2023 11:07:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=emagii.com; s=default; t=1676110072; bh=9XGn9JaCD+l9aMdWD4jKf3UB7a6FWOOcC5Vgj8Q3ZAk=; h=From:To:Subject; b=uAYJGb5TVTozEg4k2xDUO7kVRSnbmJyb0upWHvEnniDzyCys1sN5tEaRNK4HCv12b 5wItSEB/dN8WbUmch/UWcHXBYCInPcI4afTl8mLf+ncBG7ZS00dqVV7CYn5ZqmudG7 9TFWohWT0uiU5tNY7VRx93Ily4HdJ4rQGszvst84= Authentication-Results: emagii.beebytevps.io; spf=pass (sender IP is 84.55.68.216) smtp.mailfrom=u-boot@emagii.com smtp.helo=valinor.ownit.se Received-SPF: pass (emagii.beebytevps.io: connection is authenticated) From: u-boot@emagii.com To: u-boot@lists.denx.de Cc: marex@denx.de, monstr@monstr.eu, sjg@chromium.org Subject: [PATCH 0/4] FPGAs as Memory Technology Devices in U-Boot Date: Sat, 11 Feb 2023 11:07:39 +0100 Message-Id: <20230211100743.12087-1-u-boot@emagii.com> X-Mailer: git-send-email 2.17.1 X-PPP-Message-ID: <167611007220.3658108.13266718463948998001@localhost.localdomain> X-PPP-Vhost: emagii.com X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: u-boot@emagii.com Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean As shown at a presentation in the recent OpenEmbedded Workshop, it is possible to configure an FPGA in Passive Serial mode using a standard SPI controller, each FPGA getting its own chipselect. https://pretalx.com/openembedded-workshop-2023/talk/D3AQ3R/ This allows you to add the FPGA to the devicetree and to use standard MTD commands, instead of the FPGA commands. I.E: The SPI portion is &spi1 { u-boot,dm-spl; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; num-cs = <4>; /* Needed for GPIO cs */ cs-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>, /* D18,0:12 uart1_ctsn.spi1_cs0 */ <&gpio0 13 GPIO_ACTIVE_LOW>, /* D17,0:13 uart1_rtsn.spi1_cs1 */ <&gpio0 17 GPIO_ACTIVE_LOW>, /* K15,0:17 mii_txd2.spi1_cs2 */ <&gpio0 16 GPIO_ACTIVE_LOW>; /* J18,0:16 mii_txd3.spi1_cs3 */ spi-max-frequency = <10000000>; ; gpio_spi0: gpio_spi@0 {...} gpio_spi1: gpio_spi@1 {...} spi-fpga-cfg@2 {...} /* FPGA #1 */ spy-fpga-cfg@3 {...} /* FPGA #2 */ }; The FPGA part is. spi-fpga-cfg@2 { /* Intel Cyclone 10, 10CL010 */ #address-cells = <1>; #size-cells = <1>; compatible = "intel,cyclone10"; reg = <2>; /* Chip select 2 */ spi-max-frequency = <10000000>; fpga = "spif"; /* Installed as /dev/spif */ config-size = <368011>; nconfig-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* ,3:15 */ nstat-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* ,3:19 */ confd-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; /* ,3:18 */ crc-error-gpios= <&gpio2 1 GPIO_ACTIVE_HIGH>; /* ,2:01 */ partition@0 { label = "spi-fpga"; reg = <0x0000000 0x8000>; }; }; To configure the FPGA, you load the config info into RAM and write it to the FPGA. U-BOOT> mtd read spi1 ${loadaddr} 0 ${filesize} # read from SPI U-BOOT> mtd write fpga0 ${loadaddr} 0 ${filesize} # configure FPGA A driver will pulse the nCONFIG pin of the FPGA, do an SPI transfer and then check the FPGA status outputs. Since the MTD command set can be used (and is needed anyway) the FPGA command set can be removed from the U-Boot both simplifying the user interface and reducing code size of the u-boot image. It relies on the (hopefully) existing SPI driver for the chip in u-boot so it should be easy to use in most systems (as long as the H/W is designed for it) A linux driver, using the same principle would allow the FPGA to be configured using a simple statement. $ cat > /dev/fpga The approach has been tested on a development board using an AM335x and 2 x Cyclone 10. The changes needed are * adding the FPGA class in mtd-abi.h * The "mtd" command hardwires the transfer to be RAW and no OOB. * A driver wrapping the control signals around an SPI transfer 1.Claim SPI bus 2.Pulse nCONFIG low for 40 us, 3.Wait for nSTATUS high 4.Transfer bitstream using U-Boot SPI transfer 5.Release SPI bus 6.Wait until CONFIG_DONE (or error on nSTATUS) [PATCH 1/4] include/mtd/mtd-abi.h: Add FPGA as MTD device [PATCH 2/4] cmd/mtd.c: Support FPGAs in mtd command [PATCH 3/4] mtd/fpga: add fpga directory to mtd (with Cyclone 10) [PATCH 4/4] mtd/Kconfig,Makefile support FPGA