Re: [PATCH V2 4/9] arm64: dts: rockchip: Sync rk356x from Linux main

Kever Yang
2023-02-22T07:32:36Z

Hi Chris,

On 2023/2/16 02:44, Jonas Karlman wrote:
> On 2023-02-13 23:27, Chris Morgan wrote:
>> From: Chris Morgan <macromorgan@hotmail.com>
>>
>> Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of
>> this writing).
>>
>> Note that this will rename the rk3568-evb to rk3568-evb1-v10.
> Is the rename and sync of evb-rk3568 necessary for your use case?
>
> I tend to abuse the evb variants as "minimal" soc defconfig. They
> usually contain minimal needed to boot any board following the reference
> design from sd or emmc.
>
> Using the current evb-rk3568_defconfig and rk3568-evb.dts I can boot,
> load atf and start linux on all my rk3566/rk3568 boards. Not sure that
> will continue to be possible after these changes.

There are many SBC boards copy the core logic from evb, so the
evb-rk3568 config can

make many boards boot. We can keep evb-rk3568_defconfig before there in
another

rk3568 evb available on the tree.

For others:

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,

- Kever

> Regards,
> Jonas
>
>> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>> ---
>> arch/arm/dts/Makefile | 2 +-
>> arch/arm/dts/rk3568-evb.dts | 79 --
>> ...-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} | 0
>> arch/arm/dts/rk3568-evb1-v10.dts | 692 ++++++++++++++++++
>> arch/arm/dts/rk3568.dtsi | 122 +++
>> arch/arm/dts/rk356x.dtsi | 182 ++++-
>> ...68_defconfig => evb1-v10-rk3568_defconfig} | 4 +-
>> 7 files changed, 985 insertions(+), 96 deletions(-)
>> delete mode 100644 arch/arm/dts/rk3568-evb.dts
>> rename arch/arm/dts/{rk3568-evb-u-boot.dtsi => rk3568-evb1-v10-u-boot.dtsi} (100%)
>> create mode 100644 arch/arm/dts/rk3568-evb1-v10.dts
>> rename configs/{evb-rk3568_defconfig => evb1-v10-rk3568_defconfig} (94%)
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index 9d647b9639..56e0543bd2 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -165,7 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
>> rk3399pro-rock-pi-n10.dtb
>>
>> dtb-$(CONFIG_ROCKCHIP_RK3568) += \
>> - rk3568-evb.dtb
>> + rk3568-evb1-v10.dtb
>>
>> dtb-$(CONFIG_ROCKCHIP_RV1108) += \
>> rv1108-elgin-r1.dtb \
>> diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts
>> deleted file mode 100644
>> index 6978655709..0000000000
>> --- a/arch/arm/dts/rk3568-evb.dts
>> +++ /dev/null
>> @@ -1,79 +0,0 @@
>> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> -/*
>> - * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
>> - *
>> - */
>> -
>> -/dts-v1/;
>> -#include <dt-bindings/gpio/gpio.h>
>> -#include <dt-bindings/pinctrl/rockchip.h>
>> -#include "rk3568.dtsi"
>> -
>> -/ {
>> - model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
>> - compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
>> -
>> - chosen: chosen {
>> - stdout-path = "serial2:1500000n8";
>> - };
>> -
>> - dc_12v: dc-12v {
>> - compatible = "regulator-fixed";
>> - regulator-name = "dc_12v";
>> - regulator-always-on;
>> - regulator-boot-on;
>> - regulator-min-microvolt = <12000000>;
>> - regulator-max-microvolt = <12000000>;
>> - };
>> -
>> - vcc3v3_sys: vcc3v3-sys {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vcc3v3_sys";
>> - regulator-always-on;
>> - regulator-boot-on;
>> - regulator-min-microvolt = <3300000>;
>> - regulator-max-microvolt = <3300000>;
>> - vin-supply = <&dc_12v>;
>> - };
>> -
>> - vcc5v0_sys: vcc5v0-sys {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vcc5v0_sys";
>> - regulator-always-on;
>> - regulator-boot-on;
>> - regulator-min-microvolt = <5000000>;
>> - regulator-max-microvolt = <5000000>;
>> - vin-supply = <&dc_12v>;
>> - };
>> -
>> - vcc3v3_lcd0_n: vcc3v3-lcd0-n {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vcc3v3_lcd0_n";
>> - regulator-boot-on;
>> -
>> - regulator-state-mem {
>> - regulator-off-in-suspend;
>> - };
>> - };
>> -
>> - vcc3v3_lcd1_n: vcc3v3-lcd1-n {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vcc3v3_lcd1_n";
>> - regulator-boot-on;
>> -
>> - regulator-state-mem {
>> - regulator-off-in-suspend;
>> - };
>> - };
>> -};
>> -
>> -&sdhci {
>> - bus-width = <8>;
>> - max-frequency = <200000000>;
>> - non-removable;
>> - status = "okay";
>> -};
>> -
>> -&uart2 {
>> - status = "okay";
>> -};
>> diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
>> similarity index 100%
>> rename from arch/arm/dts/rk3568-evb-u-boot.dtsi
>> rename to arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
>> diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
>> new file mode 100644
>> index 0000000000..674792567f
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3568-evb1-v10.dts
>> @@ -0,0 +1,692 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/leds/common.h>
>> +#include <dt-bindings/pinctrl/rockchip.h>
>> +#include <dt-bindings/soc/rockchip,vop2.h>
>> +#include "rk3568.dtsi"
>> +
>> +/ {
>> + model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
>> + compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
>> +
>> + aliases {
>> + ethernet0 = &gmac0;
>> + ethernet1 = &gmac1;
>> + mmc0 = &sdmmc0;
>> + mmc1 = &sdhci;
>> + };
>> +
>> + chosen: chosen {
>> + stdout-path = "serial2:1500000n8";
>> + };
>> +
>> + dc_12v: dc-12v {
>> + compatible = "regulator-fixed";
>> + regulator-name = "dc_12v";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <12000000>;
>> + regulator-max-microvolt = <12000000>;
>> + };
>> +
>> + hdmi-con {
>> + compatible = "hdmi-connector";
>> + type = "a";
>> +
>> + port {
>> + hdmi_con_in: endpoint {
>> + remote-endpoint = <&hdmi_out_con>;
>> + };
>> + };
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> +
>> + led_work: led-0 {
>> + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
>> + function = LED_FUNCTION_HEARTBEAT;
>> + color = <LED_COLOR_ID_BLUE>;
>> + linux,default-trigger = "heartbeat";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&led_work_en>;
>> + };
>> + };
>> +
>> + rk809-sound {
>> + compatible = "simple-audio-card";
>> + simple-audio-card,format = "i2s";
>> + simple-audio-card,name = "Analog RK809";
>> + simple-audio-card,mclk-fs = <256>;
>> +
>> + simple-audio-card,cpu {
>> + sound-dai = <&i2s1_8ch>;
>> + };
>> + simple-audio-card,codec {
>> + sound-dai = <&rk809>;
>> + };
>> + };
>> +
>> + vcc3v3_sys: vcc3v3-sys {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3_sys";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + vin-supply = <&dc_12v>;
>> + };
>> +
>> + vcc5v0_sys: vcc5v0-sys {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc5v0_sys";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + vin-supply = <&dc_12v>;
>> + };
>> +
>> + vcc5v0_usb: vcc5v0-usb {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc5v0_usb";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + vin-supply = <&dc_12v>;
>> + };
>> +
>> + vcc5v0_usb_host: vcc5v0-usb-host {
>> + compatible = "regulator-fixed";
>> + enable-active-high;
>> + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vcc5v0_usb_host_en>;
>> + regulator-name = "vcc5v0_usb_host";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + vin-supply = <&vcc5v0_usb>;
>> + };
>> +
>> + vcc5v0_usb_otg: vcc5v0-usb-otg {
>> + compatible = "regulator-fixed";
>> + enable-active-high;
>> + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vcc5v0_usb_otg_en>;
>> + regulator-name = "vcc5v0_usb_otg";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + vin-supply = <&vcc5v0_usb>;
>> + };
>> +
>> + vcc3v3_lcd0_n: vcc3v3-lcd0-n {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3_lcd0_n";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + enable-active-high;
>> + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
>> + vin-supply = <&vcc3v3_sys>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vcc3v3_lcd0_n_en>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc3v3_lcd1_n: vcc3v3-lcd1-n {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3_lcd1_n";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + enable-active-high;
>> + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
>> + vin-supply = <&vcc3v3_sys>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vcc3v3_lcd1_n_en>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +};
>> +
>> +&combphy0 {
>> + status = "okay";
>> +};
>> +
>> +&combphy1 {
>> + status = "okay";
>> +};
>> +
>> +&cpu0 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&cpu1 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&cpu2 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&cpu3 {
>> + cpu-supply = <&vdd_cpu>;
>> +};
>> +
>> +&gmac0 {
>> + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
>> + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
>> + assigned-clock-rates = <0>, <125000000>;
>> + clock_in_out = "output";
>> + phy-handle = <&rgmii_phy0>;
>> + phy-mode = "rgmii-id";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gmac0_miim
>> + &gmac0_tx_bus2
>> + &gmac0_rx_bus2
>> + &gmac0_rgmii_clk
>> + &gmac0_rgmii_bus>;
>> + status = "okay";
>> +};
>> +
>> +&gmac1 {
>> + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
>> + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
>> + assigned-clock-rates = <0>, <125000000>;
>> + clock_in_out = "output";
>> + phy-handle = <&rgmii_phy1>;
>> + phy-mode = "rgmii-id";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gmac1m1_miim
>> + &gmac1m1_tx_bus2
>> + &gmac1m1_rx_bus2
>> + &gmac1m1_rgmii_clk
>> + &gmac1m1_rgmii_bus>;
>> + status = "okay";
>> +};
>> +
>> +&gpu {
>> + mali-supply = <&vdd_gpu>;
>> + status = "okay";
>> +};
>> +
>> +&hdmi {
>> + avdd-0v9-supply = <&vdda0v9_image>;
>> + avdd-1v8-supply = <&vcca1v8_image>;
>> + status = "okay";
>> +};
>> +
>> +&hdmi_in {
>> + hdmi_in_vp0: endpoint {
>> + remote-endpoint = <&vp0_out_hdmi>;
>> + };
>> +};
>> +
>> +&hdmi_out {
>> + hdmi_out_con: endpoint {
>> + remote-endpoint = <&hdmi_con_in>;
>> + };
>> +};
>> +
>> +&hdmi_sound {
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> +
>> + vdd_cpu: regulator@1c {
>> + compatible = "tcs,tcs4525";
>> + reg = <0x1c>;
>> + fcs,suspend-voltage-selector = <1>;
>> + regulator-name = "vdd_cpu";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <1150000>;
>> + regulator-ramp-delay = <2300>;
>> + vin-supply = <&vcc5v0_sys>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + rk809: pmic@20 {
>> + compatible = "rockchip,rk809";
>> + reg = <0x20>;
>> + interrupt-parent = <&gpio0>;
>> + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
>> + assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
>> + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
>> + #clock-cells = <1>;
>> + clock-names = "mclk";
>> + clocks = <&cru I2S1_MCLKOUT_TX>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
>> + rockchip,system-power-controller;
>> + #sound-dai-cells = <0>;
>> + vcc1-supply = <&vcc3v3_sys>;
>> + vcc2-supply = <&vcc3v3_sys>;
>> + vcc3-supply = <&vcc3v3_sys>;
>> + vcc4-supply = <&vcc3v3_sys>;
>> + vcc5-supply = <&vcc3v3_sys>;
>> + vcc6-supply = <&vcc3v3_sys>;
>> + vcc7-supply = <&vcc3v3_sys>;
>> + vcc8-supply = <&vcc3v3_sys>;
>> + vcc9-supply = <&vcc3v3_sys>;
>> + wakeup-source;
>> +
>> + regulators {
>> + vdd_logic: DCDC_REG1 {
>> + regulator-name = "vdd_logic";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-init-microvolt = <900000>;
>> + regulator-initial-mode = <0x2>;
>> + regulator-min-microvolt = <500000>;
>> + regulator-max-microvolt = <1350000>;
>> + regulator-ramp-delay = <6001>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdd_gpu: DCDC_REG2 {
>> + regulator-name = "vdd_gpu";
>> + regulator-always-on;
>> + regulator-init-microvolt = <900000>;
>> + regulator-initial-mode = <0x2>;
>> + regulator-min-microvolt = <500000>;
>> + regulator-max-microvolt = <1350000>;
>> + regulator-ramp-delay = <6001>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc_ddr: DCDC_REG3 {
>> + regulator-name = "vcc_ddr";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-initial-mode = <0x2>;
>> +
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + };
>> + };
>> +
>> + vdd_npu: DCDC_REG4 {
>> + regulator-name = "vdd_npu";
>> + regulator-init-microvolt = <900000>;
>> + regulator-initial-mode = <0x2>;
>> + regulator-min-microvolt = <500000>;
>> + regulator-max-microvolt = <1350000>;
>> + regulator-ramp-delay = <6001>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc_1v8: DCDC_REG5 {
>> + regulator-name = "vcc_1v8";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdda0v9_image: LDO_REG1 {
>> + regulator-name = "vdda0v9_image";
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <900000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdda_0v9: LDO_REG2 {
>> + regulator-name = "vdda_0v9";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <900000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vdda0v9_pmu: LDO_REG3 {
>> + regulator-name = "vdda0v9_pmu";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <900000>;
>> +
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <900000>;
>> + };
>> + };
>> +
>> + vccio_acodec: LDO_REG4 {
>> + regulator-name = "vccio_acodec";
>> + regulator-always-on;
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vccio_sd: LDO_REG5 {
>> + regulator-name = "vccio_sd";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc3v3_pmu: LDO_REG6 {
>> + regulator-name = "vcc3v3_pmu";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> +
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <3300000>;
>> + };
>> + };
>> +
>> + vcca_1v8: LDO_REG7 {
>> + regulator-name = "vcca_1v8";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcca1v8_pmu: LDO_REG8 {
>> + regulator-name = "vcca1v8_pmu";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + regulator-state-mem {
>> + regulator-on-in-suspend;
>> + regulator-suspend-microvolt = <1800000>;
>> + };
>> + };
>> +
>> + vcca1v8_image: LDO_REG9 {
>> + regulator-name = "vcca1v8_image";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc_3v3: SWITCH_REG1 {
>> + regulator-name = "vcc_3v3";
>> + regulator-always-on;
>> + regulator-boot-on;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + vcc3v3_sd: SWITCH_REG2 {
>> + regulator-name = "vcc3v3_sd";
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> + };
>> +
>> + codec {
>> + mic-in-differential;
>> + };
>> + };
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> +
>> + touchscreen0: goodix@14 {
>> + compatible = "goodix,gt1151";
>> + reg = <0x14>;
>> + interrupt-parent = <&gpio0>;
>> + interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
>> + AVDD28-supply = <&vcc3v3_lcd0_n>;
>> + irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&touch_int &touch_rst>;
>> + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
>> + VDDIO-supply = <&vcc3v3_lcd0_n>;
>> + };
>> +};
>> +
>> +&i2s0_8ch {
>> + status = "okay";
>> +};
>> +
>> +&i2s1_8ch {
>> + rockchip,trcm-sync-tx-only;
>> + status = "okay";
>> +};
>> +
>> +&mdio0 {
>> + rgmii_phy0: ethernet-phy@0 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <0x0>;
>> + reset-assert-us = <20000>;
>> + reset-deassert-us = <100000>;
>> + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
>> + };
>> +};
>> +
>> +&mdio1 {
>> + rgmii_phy1: ethernet-phy@0 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <0x0>;
>> + reset-assert-us = <20000>;
>> + reset-deassert-us = <100000>;
>> + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
>> + };
>> +};
>> +
>> +&pinctrl {
>> + display {
>> + vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en {
>> + rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>;
>> + };
>> + vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en {
>> + rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + leds {
>> + led_work_en: led_work_en {
>> + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + pmic {
>> + pmic_int: pmic_int {
>> + rockchip,pins =
>> + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
>> + };
>> + };
>> +
>> + touchscreen {
>> + touch_int: touch_int {
>> + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
>> + };
>> + touch_rst: touch_rst {
>> + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +
>> + usb {
>> + vcc5v0_usb_host_en: vcc5v0_usb_host_en {
>> + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
>> + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
>> + };
>> + };
>> +};
>> +
>> +&pmu_io_domains {
>> + pmuio1-supply = <&vcc3v3_pmu>;
>> + pmuio2-supply = <&vcc3v3_pmu>;
>> + vccio1-supply = <&vccio_acodec>;
>> + vccio2-supply = <&vcc_1v8>;
>> + vccio3-supply = <&vccio_sd>;
>> + vccio4-supply = <&vcc_1v8>;
>> + vccio5-supply = <&vcc_3v3>;
>> + vccio6-supply = <&vcc_1v8>;
>> + vccio7-supply = <&vcc_3v3>;
>> + status = "okay";
>> +};
>> +
>> +&saradc {
>> + vref-supply = <&vcca_1v8>;
>> + status = "okay";
>> +};
>> +
>> +&sdhci {
>> + bus-width = <8>;
>> + max-frequency = <200000000>;
>> + non-removable;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
>> + status = "okay";
>> +};
>> +
>> +&sdmmc0 {
>> + bus-width = <4>;
>> + cap-sd-highspeed;
>> + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
>> + disable-wp;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
>> + sd-uhs-sdr104;
>> + vmmc-supply = <&vcc3v3_sd>;
>> + vqmmc-supply = <&vccio_sd>;
>> + status = "okay";
>> +};
>> +
>> +&tsadc {
>> + rockchip,hw-tshut-mode = <1>;
>> + rockchip,hw-tshut-polarity = <0>;
>> + status = "okay";
>> +};
>> +
>> +&uart2 {
>> + status = "okay";
>> +};
>> +
>> +&usb_host0_ehci {
>> + status = "okay";
>> +};
>> +
>> +&usb_host0_ohci {
>> + status = "okay";
>> +};
>> +
>> +&usb_host0_xhci {
>> + extcon = <&usb2phy0>;
>> + status = "okay";
>> +};
>> +
>> +&usb_host1_ehci {
>> + status = "okay";
>> +};
>> +
>> +&usb_host1_ohci {
>> + status = "okay";
>> +};
>> +
>> +&usb_host1_xhci {
>> + status = "okay";
>> +};
>> +
>> +&usb2phy0 {
>> + status = "okay";
>> +};
>> +
>> +&usb2phy0_host {
>> + phy-supply = <&vcc5v0_usb_host>;
>> + status = "okay";
>> +};
>> +
>> +&usb2phy0_otg {
>> + phy-supply = <&vcc5v0_usb_otg>;
>> + status = "okay";
>> +};
>> +
>> +&usb2phy1 {
>> + status = "okay";
>> +};
>> +
>> +&usb2phy1_host {
>> + phy-supply = <&vcc5v0_usb_host>;
>> + status = "okay";
>> +};
>> +
>> +&usb2phy1_otg {
>> + phy-supply = <&vcc5v0_usb_host>;
>> + status = "okay";
>> +};
>> +
>> +&vop {
>> + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
>> + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
>> + status = "okay";
>> +};
>> +
>> +&vop_mmu {
>> + status = "okay";
>> +};
>> +
>> +&vp0 {
>> + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
>> + reg = <ROCKCHIP_VOP2_EP_HDMI0>;
>> + remote-endpoint = <&hdmi_in_vp0>;
>> + };
>> +};
>> diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
>> index 2bdf8c7e97..ba67b58f05 100644
>> --- a/arch/arm/dts/rk3568.dtsi
>> +++ b/arch/arm/dts/rk3568.dtsi
>> @@ -42,6 +42,128 @@
>> reg = <0x0 0xfe190200 0x0 0x20>;
>> };
>>
>> + pcie30_phy_grf: syscon@fdcb8000 {
>> + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
>> + reg = <0x0 0xfdcb8000 0x0 0x10000>;
>> + };
>> +
>> + pcie30phy: phy@fe8c0000 {
>> + compatible = "rockchip,rk3568-pcie3-phy";
>> + reg = <0x0 0xfe8c0000 0x0 0x20000>;
>> + #phy-cells = <0>;
>> + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
>> + <&cru PCLK_PCIE30PHY>;
>> + clock-names = "refclk_m", "refclk_n", "pclk";
>> + resets = <&cru SRST_PCIE30PHY>;
>> + reset-names = "phy";
>> + rockchip,phy-grf = <&pcie30_phy_grf>;
>> + status = "disabled";
>> + };
>> +
>> + pcie3x1: pcie@fe270000 {
>> + compatible = "rockchip,rk3568-pcie";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + bus-range = <0x0 0xf>;
>> + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
>> + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
>> + <&cru CLK_PCIE30X1_AUX_NDFT>;
>> + clock-names = "aclk_mst", "aclk_slv",
>> + "aclk_dbi", "pclk", "aux";
>> + device_type = "pci";
>> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
>> + <0 0 0 2 &pcie3x1_intc 1>,
>> + <0 0 0 3 &pcie3x1_intc 2>,
>> + <0 0 0 4 &pcie3x1_intc 3>;
>> + linux,pci-domain = <1>;
>> + num-ib-windows = <6>;
>> + num-ob-windows = <2>;
>> + max-link-speed = <3>;
>> + msi-map = <0x0 &gic 0x1000 0x1000>;
>> + num-lanes = <1>;
>> + phys = <&pcie30phy>;
>> + phy-names = "pcie-phy";
>> + power-domains = <&power RK3568_PD_PIPE>;
>> + reg = <0x3 0xc0400000 0x0 0x00400000>,
>> + <0x0 0xfe270000 0x0 0x00010000>,
>> + <0x3 0x7f000000 0x0 0x01000000>;
>> + ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
>> + <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
>> + reg-names = "dbi", "apb", "config";
>> + resets = <&cru SRST_PCIE30X1_POWERUP>;
>> + reset-names = "pipe";
>> + /* bifurcation; lane1 when using 1+1 */
>> + status = "disabled";
>> +
>> + pcie3x1_intc: legacy-interrupt-controller {
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
>> + };
>> + };
>> +
>> + pcie3x2: pcie@fe280000 {
>> + compatible = "rockchip,rk3568-pcie";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + bus-range = <0x0 0xf>;
>> + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
>> + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
>> + <&cru CLK_PCIE30X2_AUX_NDFT>;
>> + clock-names = "aclk_mst", "aclk_slv",
>> + "aclk_dbi", "pclk", "aux";
>> + device_type = "pci";
>> + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
>> + <0 0 0 2 &pcie3x2_intc 1>,
>> + <0 0 0 3 &pcie3x2_intc 2>,
>> + <0 0 0 4 &pcie3x2_intc 3>;
>> + linux,pci-domain = <2>;
>> + num-ib-windows = <6>;
>> + num-ob-windows = <2>;
>> + max-link-speed = <3>;
>> + msi-map = <0x0 &gic 0x2000 0x1000>;
>> + num-lanes = <2>;
>> + phys = <&pcie30phy>;
>> + phy-names = "pcie-phy";
>> + power-domains = <&power RK3568_PD_PIPE>;
>> + reg = <0x3 0xc0800000 0x0 0x00400000>,
>> + <0x0 0xfe280000 0x0 0x00010000>,
>> + <0x3 0xbf000000 0x0 0x01000000>;
>> + ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
>> + <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
>> + reg-names = "dbi", "apb", "config";
>> + resets = <&cru SRST_PCIE30X2_POWERUP>;
>> + reset-names = "pipe";
>> + /* bifurcation; lane0 when using 1+1 */
>> + status = "disabled";
>> +
>> + pcie3x2_intc: legacy-interrupt-controller {
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
>> + };
>> + };
>> +
>> gmac0: ethernet@fe2a0000 {
>> compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
>> reg = <0x0 0xfe2a0000 0x0 0x10000>;
>> diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
>> index 319981c3e9..5706c3e24f 100644
>> --- a/arch/arm/dts/rk356x.dtsi
>> +++ b/arch/arm/dts/rk356x.dtsi
>> @@ -592,6 +592,46 @@
>> status = "disabled";
>> };
>>
>> + vpu: video-codec@fdea0400 {
>> + compatible = "rockchip,rk3568-vpu";
>> + reg = <0x0 0xfdea0000 0x0 0x800>;
>> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
>> + clock-names = "aclk", "hclk";
>> + iommus = <&vdpu_mmu>;
>> + power-domains = <&power RK3568_PD_VPU>;
>> + };
>> +
>> + vdpu_mmu: iommu@fdea0800 {
>> + compatible = "rockchip,rk3568-iommu";
>> + reg = <0x0 0xfdea0800 0x0 0x40>;
>> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "aclk", "iface";
>> + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
>> + power-domains = <&power RK3568_PD_VPU>;
>> + #iommu-cells = <0>;
>> + };
>> +
>> + vepu: video-codec@fdee0000 {
>> + compatible = "rockchip,rk3568-vepu";
>> + reg = <0x0 0xfdee0000 0x0 0x800>;
>> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
>> + clock-names = "aclk", "hclk";
>> + iommus = <&vepu_mmu>;
>> + power-domains = <&power RK3568_PD_RGA>;
>> + };
>> +
>> + vepu_mmu: iommu@fdee0800 {
>> + compatible = "rockchip,rk3568-iommu";
>> + reg = <0x0 0xfdee0800 0x0 0x40>;
>> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
>> + clock-names = "aclk", "iface";
>> + power-domains = <&power RK3568_PD_RGA>;
>> + #iommu-cells = <0>;
>> + };
>> +
>> sdmmc2: mmc@fe000000 {
>> compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
>> reg = <0x0 0xfe000000 0x0 0x4000>;
>> @@ -699,6 +739,62 @@
>> status = "disabled";
>> };
>>
>> + dsi0: dsi@fe060000 {
>> + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
>> + reg = <0x00 0xfe060000 0x00 0x10000>;
>> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "pclk", "hclk";
>> + clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
>> + phy-names = "dphy";
>> + phys = <&dsi_dphy0>;
>> + power-domains = <&power RK3568_PD_VO>;
>> + reset-names = "apb";
>> + resets = <&cru SRST_P_DSITX_0>;
>> + rockchip,grf = <&grf>;
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + dsi0_in: port@0 {
>> + reg = <0>;
>> + };
>> +
>> + dsi0_out: port@1 {
>> + reg = <1>;
>> + };
>> + };
>> + };
>> +
>> + dsi1: dsi@fe070000 {
>> + compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
>> + reg = <0x0 0xfe070000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "pclk", "hclk";
>> + clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
>> + phy-names = "dphy";
>> + phys = <&dsi_dphy1>;
>> + power-domains = <&power RK3568_PD_VO>;
>> + reset-names = "apb";
>> + resets = <&cru SRST_P_DSITX_1>;
>> + rockchip,grf = <&grf>;
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + dsi1_in: port@0 {
>> + reg = <0>;
>> + };
>> +
>> + dsi1_out: port@1 {
>> + reg = <1>;
>> + };
>> + };
>> + };
>> +
>> hdmi: hdmi@fe0a0000 {
>> compatible = "rockchip,rk3568-dw-hdmi";
>> reg = <0x0 0xfe0a0000 0x0 0x20000>;
>> @@ -953,20 +1049,6 @@
>> status = "disabled";
>> };
>>
>> - spdif: spdif@fe460000 {
>> - compatible = "rockchip,rk3568-spdif";
>> - reg = <0x0 0xfe460000 0x0 0x1000>;
>> - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
>> - clock-names = "mclk", "hclk";
>> - clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
>> - dmas = <&dmac1 1>;
>> - dma-names = "tx";
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&spdifm0_tx>;
>> - #sound-dai-cells = <0>;
>> - status = "disabled";
>> - };
>> -
>> i2s0_8ch: i2s@fe400000 {
>> compatible = "rockchip,rk3568-i2s-tdm";
>> reg = <0x0 0xfe400000 0x0 0x1000>;
>> @@ -1009,6 +1091,28 @@
>> status = "disabled";
>> };
>>
>> + i2s2_2ch: i2s@fe420000 {
>> + compatible = "rockchip,rk3568-i2s-tdm";
>> + reg = <0x0 0xfe420000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
>> + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
>> + assigned-clock-rates = <1188000000>;
>> + clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
>> + clock-names = "mclk_tx", "mclk_rx", "hclk";
>> + dmas = <&dmac1 4>, <&dmac1 5>;
>> + dma-names = "tx", "rx";
>> + resets = <&cru SRST_M_I2S2_2CH>;
>> + reset-names = "m";
>> + rockchip,grf = <&grf>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2s2m0_sclktx
>> + &i2s2m0_lrcktx
>> + &i2s2m0_sdi
>> + &i2s2m0_sdo>;
>> + #sound-dai-cells = <0>;
>> + status = "disabled";
>> + };
>> +
>> i2s3_2ch: i2s@fe430000 {
>> compatible = "rockchip,rk3568-i2s-tdm";
>> reg = <0x0 0xfe430000 0x0 0x1000>;
>> @@ -1046,6 +1150,20 @@
>> status = "disabled";
>> };
>>
>> + spdif: spdif@fe460000 {
>> + compatible = "rockchip,rk3568-spdif";
>> + reg = <0x0 0xfe460000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
>> + clock-names = "mclk", "hclk";
>> + clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
>> + dmas = <&dmac1 1>;
>> + dma-names = "tx";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&spdifm0_tx>;
>> + #sound-dai-cells = <0>;
>> + status = "disabled";
>> + };
>> +
>> dmac0: dma-controller@fe530000 {
>> compatible = "arm,pl330", "arm,primecell";
>> reg = <0x0 0xfe530000 0x0 0x4000>;
>> @@ -1594,6 +1712,42 @@
>> status = "disabled";
>> };
>>
>> + csi_dphy: phy@fe870000 {
>> + compatible = "rockchip,rk3568-csi-dphy";
>> + reg = <0x0 0xfe870000 0x0 0x10000>;
>> + clocks = <&cru PCLK_MIPICSIPHY>;
>> + clock-names = "pclk";
>> + #phy-cells = <0>;
>> + resets = <&cru SRST_P_MIPICSIPHY>;
>> + reset-names = "apb";
>> + rockchip,grf = <&grf>;
>> + status = "disabled";
>> + };
>> +
>> + dsi_dphy0: mipi-dphy@fe850000 {
>> + compatible = "rockchip,rk3568-dsi-dphy";
>> + reg = <0x0 0xfe850000 0x0 0x10000>;
>> + clock-names = "ref", "pclk";
>> + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
>> + #phy-cells = <0>;
>> + power-domains = <&power RK3568_PD_VO>;
>> + reset-names = "apb";
>> + resets = <&cru SRST_P_MIPIDSIPHY0>;
>> + status = "disabled";
>> + };
>> +
>> + dsi_dphy1: mipi-dphy@fe860000 {
>> + compatible = "rockchip,rk3568-dsi-dphy";
>> + reg = <0x0 0xfe860000 0x0 0x10000>;
>> + clock-names = "ref", "pclk";
>> + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
>> + #phy-cells = <0>;
>> + power-domains = <&power RK3568_PD_VO>;
>> + reset-names = "apb";
>> + resets = <&cru SRST_P_MIPIDSIPHY1>;
>> + status = "disabled";
>> + };
>> +
>> usb2phy0: usb2phy@fe8a0000 {
>> compatible = "rockchip,rk3568-usb2phy";
>> reg = <0x0 0xfe8a0000 0x0 0x10000>;
>> diff --git a/configs/evb-rk3568_defconfig b/configs/evb1-v10-rk3568_defconfig
>> similarity index 94%
>> rename from configs/evb-rk3568_defconfig
>> rename to configs/evb1-v10-rk3568_defconfig
>> index a76d924d38..7ca1a35246 100644
>> --- a/configs/evb-rk3568_defconfig
>> +++ b/configs/evb1-v10-rk3568_defconfig
>> @@ -6,7 +6,7 @@ CONFIG_TEXT_BASE=0x00a00000
>> CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> CONFIG_NR_DRAM_BANKS=2
>> -CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
>> +CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb1-v10"
>> CONFIG_ROCKCHIP_RK3568=y
>> CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
>> CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
>> @@ -23,7 +23,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
>> CONFIG_FIT=y
>> CONFIG_FIT_VERBOSE=y
>> CONFIG_SPL_LOAD_FIT=y
>> -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
>> # CONFIG_DISPLAY_CPUINFO is not set
>> CONFIG_DISPLAY_BOARDINFO_LATE=y
>> CONFIG_SPL_MAX_SIZE=0x20000