From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1514C636CC for ; Mon, 13 Feb 2023 22:29:32 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C07008583D; Mon, 13 Feb 2023 23:28:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P9gUdoku"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 21EB780BAD; Mon, 13 Feb 2023 23:28:19 +0100 (CET) Received: from mail-oi1-x22c.google.com (mail-oi1-x22c.google.com [IPv6:2607:f8b0:4864:20::22c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0E3CE854EF for ; Mon, 13 Feb 2023 23:27:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=macroalpha82@gmail.com Received: by mail-oi1-x22c.google.com with SMTP id bd6so11543277oib.6 for ; Mon, 13 Feb 2023 14:27:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kXgrjh80iORcyBGafIZdzInB17QF66oaEHRIKX9TBww=; b=P9gUdokuApzHDg9xQOhOQQ3rJw9J8x4xruRC65DdoEIJQai2fEDZP5er608FPE0IMr 2jZJItQVVRfuYGY4pnzuV23t8ZENgQWu+RGfDP/JYcfEx6mvp5wV1SWax/AY0UIN4DAg IIUPQzBg/tgImwoUYNDKmMw4aGWij9hNER9mvoT6FNePCOTftrXRC/Kpdx+rpL/FlUpW zxayy127ij2FvFpQQuKoGVyV394xpgvcSGmnmMh48y07/cj02ttcWTb9WEDat+KLu5Jd u91QKHg2y7XTQ0tzDeMgAPR9fKLdCHUgKvLqiFgaUkHARj77f30iOr0L9AYkKqHwEMkj uJ2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kXgrjh80iORcyBGafIZdzInB17QF66oaEHRIKX9TBww=; b=TAED1hvcsARAe9j20U5JwANRzF3QHF5vyoA5lFoAz2ae4uzB//LThx5XNNAEJrCSR6 A1v/2zwsvevIxzt6b9IQR/3o96PcoTTOc22RYKtUJrwlh1QOgoCs9zl26ePsxzuUe4Pr /BUZA5H7340C2eAZf5K7SUFIzQBGAPGPCkc5q5IeN9mpKGPzSE2bX8X8N2o0TkYkZSu6 n+XHzZn4CBVGHSkSszc2pGuuNbcX5OQYbjCHwlMcsZX5MmLt8TNy+Luu7NEElvASkJyX 4JPx3vhl6lY7NkErWgnh0GQ1sGOOnAk37/73bQZY81ORAyxng3wMg3fV7EQHkKJ8/p9q flUA== X-Gm-Message-State: AO0yUKU7lrl8TPozo9lmlLIwVGppGdLki9L9H+k1lET1Q1RceYWzzAL0 WcXUU3qUjHo9kZ8MoKysYpaEX49SjME= X-Google-Smtp-Source: AK7set8kH3oit2LuGZzv5oNqLn5rdqXq+aLPiuG+vh5ttLxMRABweUMqdEh7tR4Ed+rWiNF2PSkKGg== X-Received: by 2002:a05:6808:df6:b0:364:ebf2:735f with SMTP id g54-20020a0568080df600b00364ebf2735fmr223449oic.24.1676327276034; Mon, 13 Feb 2023 14:27:56 -0800 (PST) Received: from localhost.localdomain ([76.244.6.13]) by smtp.gmail.com with ESMTPSA id bf16-20020a056808191000b0037d790218c1sm3044085oib.9.2023.02.13.14.27.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Feb 2023 14:27:55 -0800 (PST) From: Chris Morgan To: u-boot@lists.denx.de Cc: heiko@sntech.de, sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com, chenjh@rock-chips.com, pgwipeout@gmail.com, heiko.stuebner@theobroma-systems.com, Chris Morgan Subject: [PATCH V2 6/9] rockchip: rk3568: enable automatic power savings Date: Mon, 13 Feb 2023 16:27:39 -0600 Message-Id: <20230213222742.135093-7-macroalpha82@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230213222742.135093-1-macroalpha82@gmail.com> References: <20230213222742.135093-1-macroalpha82@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Chris Morgan It enables automatic clock gating on idle, disables the eDP phy by default, and sets the core pvtpll ring length. It is reported this lowers the temperature on at least one SoC by 7C. Signed-off-by: Peter Geis Signed-off-by: Chris Morgan --- arch/arm/mach-rockchip/rk3568/rk3568.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index a2d59abc26..4a08820a09 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -24,6 +24,16 @@ #define SGRF_SOC_CON4 0x10 #define EMMC_HPROT_SECURE_CTRL 0x03 #define SDMMC0_HPROT_SECURE_CTRL 0x01 + +#define PMU_BASE_ADDR 0xfdd90000 +#define PMU_NOC_AUTO_CON0 (0x70) +#define PMU_NOC_AUTO_CON1 (0x74) +#define EDP_PHY_GRF_BASE 0xfdcb0000 +#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00) +#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28) +#define CPU_GRF_BASE 0xfdc30000 +#define GRF_CORE_PVTPLL_CON0 (0x10) + /* PMU_GRF_GPIO0D_IOMUX_L */ enum { GPIO0D1_SHIFT = 4, @@ -98,6 +108,20 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { #ifdef CONFIG_SPL_BUILD + /* + * When perform idle operation, corresponding clock can + * be opened or gated automatically. + */ + writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); + writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); + + /* Disable eDP phy by default */ + writel(0x00070007, EDP_PHY_GRF_CON10); + writel(0x0ff10ff1, EDP_PHY_GRF_CON0); + + /* Set core pvtpll ring length */ + writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0); + /* Set the emmc sdmmc0 to secure */ rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11 | SDMMC0_HPROT_SECURE_CTRL << 4)); -- 2.34.1