From: "Paweł Anikiel" <pan@semihalf.com>
To: u-boot@lists.denx.de, marex@denx.de,
simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com
Cc: sjg@chromium.org, ka@semihalf.com, mw@semihalf.com,
amstan@chromium.org, "Paweł Anikiel" <pan@semihalf.com>
Subject: [PATCH v2 RESEND 5/6] arm: dts: chameleonv3: Add 270-2 variant
Date: Tue, 21 Feb 2023 16:17:05 +0100 [thread overview]
Message-ID: <20230221151706.48065-6-pan@semihalf.com> (raw)
In-Reply-To: <20230221151706.48065-1-pan@semihalf.com>
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
arch/arm/dts/Makefile | 1 +
.../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi | 12 ++++++++++++
arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts | 5 +++++
3 files changed, 18 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9d647b9639..7a577deb50 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -442,6 +442,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_chameleonv3_270_2.dtb \
socfpga_arria10_chameleonv3_270_3.dtb \
socfpga_arria10_chameleonv3_480_2.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
new file mode 100644
index 0000000000..05b4485cf3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+ altr,bitstream = "fpga-270-2.itb";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
new file mode 100644
index 0000000000..bef0280212
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dtsi"
--
2.39.2.637.g21b0678d19-goog
next prev parent reply other threads:[~2023-02-21 15:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 15:17 [PATCH v2 RESEND 0/6] Update Chameleon v3 configuration Paweł Anikiel
2023-02-21 15:17 ` [PATCH v2 RESEND 1/6] socfpga: chameleonv3: Enable ext4 in SPL Paweł Anikiel
2023-02-21 15:17 ` [PATCH v2 RESEND 2/6] socfpga: chameleonv3: Move environment to a text file Paweł Anikiel
2023-02-21 15:17 ` [PATCH v2 RESEND 3/6] arm: dts: chameleonv3: Override chameleonv3 bitstream names Paweł Anikiel
2023-02-21 15:17 ` [PATCH v2 RESEND 4/6] arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi Paweł Anikiel
2023-02-21 15:17 ` Paweł Anikiel [this message]
2023-02-21 15:17 ` [PATCH v2 RESEND 6/6] chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig Paweł Anikiel
2023-02-21 23:29 ` [PATCH v2 RESEND 0/6] Update Chameleon v3 configuration Marek Vasut
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