From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 846C0C636D7 for ; Tue, 21 Feb 2023 20:34:04 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5971B85BB2; Tue, 21 Feb 2023 21:24:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="a5TEmU6q"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D548185B66; Tue, 21 Feb 2023 21:23:59 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0709685B05 for ; Tue, 21 Feb 2023 21:22:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2523F61200; Tue, 21 Feb 2023 20:22:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE8EDC433A0; Tue, 21 Feb 2023 20:22:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1677010957; bh=e68+NGjEIQFIB9GfgjURTVNARGHzgw88anzjoc4zCfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a5TEmU6qFnXIo3cg79RzkovZe3hMKP4yEMeTVPlBKkq1UkkB3fygArUhXpKeI8ifZ nJ/pRwrRJkTxPWJ6lE1J54IIcx0kEbglL/fQ52JgY0fHmoczwPLGmDueogiWmYfU1q nmifALcdsxkoCN5lTtyzEfwFb5cL3j3e+7/D+j9Ft7hK0N35amAZSxVWhO7bHM9Umx WPxbdfYEjQZVHZ7SHym4NtodDSAeRdB90I5/hSy49SNAblgwb9P/gnI/ecIYZlOJrQ a0rOm38iRczBWr5ZKyRuD932gfYVxbwR6d3tymnubxiCbXbh0LZb5UwvWWH+VzJNcK XkeG6MkOQ6tHQ== Received: by pali.im (Postfix) id 8CCC2AA6; Tue, 21 Feb 2023 21:22:36 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: u-boot@lists.denx.de Cc: Stefan Roese , Tony Dinh , Josua Mayer Subject: [PATCH RFC u-boot-mvebu 58/59] arm: mvebu: Define SPL memory maps Date: Tue, 21 Feb 2023 21:19:24 +0100 Message-Id: <20230221201925.9644-59-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230221201925.9644-1-pali@kernel.org> References: <20230221201925.9644-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean In SPL are active memory maps set by the BootROM. Define them in cpu.h file to the correct values. Some peripherals are not mapped at all. Signed-off-by: Pali Rohár --- arch/arm/mach-mvebu/include/mach/cpu.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 906a8737a401..904e7157ba61 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -66,11 +66,21 @@ enum cpu_attrib { /* * Default Device Address MAP BAR values */ +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_ARMADA_38X +#define MBUS_PCI_MEM_BASE 0x88000000 +#define MBUS_PCI_MEM_SIZE ((3 * 128) << 20) +#else +#define MBUS_PCI_MEM_BASE 0x80000000 +#define MBUS_PCI_MEM_SIZE ((4 * 128) << 20) +#endif +#else #define MBUS_PCI_MAX_PORTS 6 #define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX #define MBUS_PCI_MEM_SIZE ((MBUS_PCI_MAX_PORTS * 128) << 20) #define MBUS_PCI_IO_BASE 0xF1100000 #define MBUS_PCI_IO_SIZE ((MBUS_PCI_MAX_PORTS * 64) << 10) +#endif #ifdef CONFIG_SPL_BUILD #define MBUS_SPI_BASE 0xD4000000 #define MBUS_SPI_SIZE (64 << 20) @@ -78,10 +88,16 @@ enum cpu_attrib { #define MBUS_SPI_BASE 0xF4000000 #define MBUS_SPI_SIZE (8 << 20) #endif +#ifndef CONFIG_SPL_BUILD #define MBUS_DFX_BASE 0xF6000000 #define MBUS_DFX_SIZE (1 << 20) +#endif #define MBUS_BOOTROM_BASE 0xF8000000 +#ifdef CONFIG_SPL_BUILD +#define MBUS_BOOTROM_SIZE (128 << 20) +#else #define MBUS_BOOTROM_SIZE (8 << 20) +#endif struct mbus_win { u32 base; -- 2.20.1