From: Minda Chen <minda.chen@starfivetech.com>
To: "Simon Glass" <sjg@chromium.org>, "Stefan Roese" <sr@denx.de>,
"Andrew Scull" <ascull@google.com>,
"Pali Rohár" <pali@kernel.org>
Cc: <u-boot@lists.denx.de>, Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>, Rick Chen <rick@andestech.com>,
Leo <ycliang@andestech.com>,
Mason Huo <mason.huo@starfivetech.com>,
Yanhong Wang <yanhong.wang@starfivetech.com>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>
Subject: [PATCH 2/4] clk: starfive: Add PCIe clocks for PCIe controller
Date: Thu, 23 Feb 2023 18:52:38 +0800 [thread overview]
Message-ID: <20230223105240.15180-3-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230223105240.15180-1-minda.chen@starfivetech.com>
From: Mason Huo <mason.huo@starfivetech.com>
Add the stg clocks for StarFive JH7110 PCIe controller.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/clk/starfive/clk-jh7110.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index a904852cab..7cfed7b847 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -305,6 +305,10 @@ static int jh7110_syscrg_init(struct udevice *dev)
clk_dm(JH7110_SYSCLK_AON_APB,
starfive_clk_fix_factor(priv->reg,
"aon_apb", "apb_bus_func", 1, 1));
+ clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
+ starfive_clk_divider(priv->reg,
+ "nocstg_bus", "bus_root",
+ OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
clk_dm(JH7110_SYSCLK_QSPI_AHB,
starfive_clk_gate(priv->reg,
"qspi_ahb", "ahb1",
@@ -342,6 +346,11 @@ static int jh7110_syscrg_init(struct udevice *dev)
starfive_clk_divider(priv->reg,
"usb_125m", "gmacusb_root",
OFFSET(JH7110_SYSCLK_USB_125M), 4));
+ clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
+ starfive_clk_gate(priv->reg,
+ "noc_bus_stg_axi",
+ "nocstg_bus",
+ OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
clk_dm(JH7110_SYSCLK_GMAC1_AHB,
starfive_clk_gate(priv->reg,
"gmac1_ahb", "ahb0",
@@ -512,6 +521,24 @@ static int jh7110_stgcrg_init(struct udevice *dev)
clk_dm(JH7110_STGCLK_USB_REFCLK,
starfive_clk_divider(priv->reg, "usb_refclk", "osc",
STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
+ clk_dm(JH7110_STGCLK_PCIE0_TL,
+ starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
+ clk_dm(JH7110_STGCLK_PCIE0_AXI,
+ starfive_clk_gate(priv->reg, "pcie0_axi_mst0", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
+ clk_dm(JH7110_STGCLK_PCIE0_APB,
+ starfive_clk_gate(priv->reg, "pcie0_apb", "stg_apb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
+ clk_dm(JH7110_STGCLK_PCIE1_TL,
+ starfive_clk_gate(priv->reg, "pcie1_tl", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
+ clk_dm(JH7110_STGCLK_PCIE1_AXI,
+ starfive_clk_gate(priv->reg, "pcie1_axi_mst0", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
+ clk_dm(JH7110_STGCLK_PCIE1_APB,
+ starfive_clk_gate(priv->reg, "pcie1_apb", "stg_apb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
return 0;
}
--
2.17.1
next prev parent reply other threads:[~2023-02-23 12:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-23 10:52 [PATCH 0/4] Add StarFive JH7110 PCIe drvier support Minda Chen
2023-02-23 10:52 ` [PATCH 1/4] starfive: pci: Add StarFive JH7110 pcie driver Minda Chen
2023-02-23 10:52 ` Minda Chen [this message]
2023-02-23 10:52 ` [PATCH 3/4] configs: starfive-jh7110: Add support for PCIe host driver Minda Chen
2023-02-23 10:52 ` [PATCH 4/4] riscv: dts: starfive: Enable PCIe host controller Minda Chen
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