From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A1AFC636D6 for ; Thu, 23 Feb 2023 12:57:36 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6E66685B2D; Thu, 23 Feb 2023 13:56:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id EF77085AF1; Thu, 23 Feb 2023 11:52:54 +0100 (CET) Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by phobos.denx.de (Postfix) with ESMTP id 3F2FD85B19 for ; Thu, 23 Feb 2023 11:52:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=minda.chen@starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id F1AB024DC94; Thu, 23 Feb 2023 18:52:43 +0800 (CST) Received: from EXMBX071.cuchost.com (172.16.6.81) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 23 Feb 2023 18:52:43 +0800 Received: from ubuntu.localdomain (113.72.147.165) by EXMBX071.cuchost.com (172.16.6.81) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 23 Feb 2023 18:52:43 +0800 From: Minda Chen To: Simon Glass , Stefan Roese , Andrew Scull , =?UTF-8?q?Pali=20Roh=C3=A1r?= CC: , Lukasz Majewski , Sean Anderson , Rick Chen , Leo , Mason Huo , Yanhong Wang , Leyfoon Tan , Minda Chen Subject: [PATCH 2/4] clk: starfive: Add PCIe clocks for PCIe controller Date: Thu, 23 Feb 2023 18:52:38 +0800 Message-ID: <20230223105240.15180-3-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230223105240.15180-1-minda.chen@starfivetech.com> References: <20230223105240.15180-1-minda.chen@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [113.72.147.165] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX071.cuchost.com (172.16.6.81) X-YovoleRuleAgent: yovoleflag X-Mailman-Approved-At: Thu, 23 Feb 2023 13:55:57 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Mason Huo Add the stg clocks for StarFive JH7110 PCIe controller. Signed-off-by: Mason Huo Signed-off-by: Minda Chen --- drivers/clk/starfive/clk-jh7110.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a904852cab..7cfed7b847 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -305,6 +305,10 @@ static int jh7110_syscrg_init(struct udevice *dev) clk_dm(JH7110_SYSCLK_AON_APB, starfive_clk_fix_factor(priv->reg, "aon_apb", "apb_bus_func", 1, 1)); + clk_dm(JH7110_SYSCLK_NOCSTG_BUS, + starfive_clk_divider(priv->reg, + "nocstg_bus", "bus_root", + OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3)); clk_dm(JH7110_SYSCLK_QSPI_AHB, starfive_clk_gate(priv->reg, "qspi_ahb", "ahb1", @@ -342,6 +346,11 @@ static int jh7110_syscrg_init(struct udevice *dev) starfive_clk_divider(priv->reg, "usb_125m", "gmacusb_root", OFFSET(JH7110_SYSCLK_USB_125M), 4)); + clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI, + starfive_clk_gate(priv->reg, + "noc_bus_stg_axi", + "nocstg_bus", + OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI))); clk_dm(JH7110_SYSCLK_GMAC1_AHB, starfive_clk_gate(priv->reg, "gmac1_ahb", "ahb0", @@ -512,6 +521,24 @@ static int jh7110_stgcrg_init(struct udevice *dev) clk_dm(JH7110_STGCLK_USB_REFCLK, starfive_clk_divider(priv->reg, "usb_refclk", "osc", STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2)); + clk_dm(JH7110_STGCLK_PCIE0_TL, + starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb", + STGOFFSET(JH7110_STGCLK_PCIE0_TL))); + clk_dm(JH7110_STGCLK_PCIE0_AXI, + starfive_clk_gate(priv->reg, "pcie0_axi_mst0", "stg_axiahb", + STGOFFSET(JH7110_STGCLK_PCIE0_AXI))); + clk_dm(JH7110_STGCLK_PCIE0_APB, + starfive_clk_gate(priv->reg, "pcie0_apb", "stg_apb", + STGOFFSET(JH7110_STGCLK_PCIE0_APB))); + clk_dm(JH7110_STGCLK_PCIE1_TL, + starfive_clk_gate(priv->reg, "pcie1_tl", "stg_axiahb", + STGOFFSET(JH7110_STGCLK_PCIE1_TL))); + clk_dm(JH7110_STGCLK_PCIE1_AXI, + starfive_clk_gate(priv->reg, "pcie1_axi_mst0", "stg_axiahb", + STGOFFSET(JH7110_STGCLK_PCIE1_AXI))); + clk_dm(JH7110_STGCLK_PCIE1_APB, + starfive_clk_gate(priv->reg, "pcie1_apb", "stg_apb", + STGOFFSET(JH7110_STGCLK_PCIE1_APB))); return 0; } -- 2.17.1