* [PATCH 0/4] Add StarFive JH7110 PCIe drvier support
@ 2023-02-23 10:52 Minda Chen
2023-02-23 10:52 ` [PATCH 1/4] starfive: pci: Add StarFive JH7110 pcie driver Minda Chen
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Minda Chen @ 2023-02-23 10:52 UTC (permalink / raw)
To: Simon Glass, Stefan Roese, Andrew Scull, Pali Rohár
Cc: u-boot, Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Mason Huo,
Yanhong Wang, Leyfoon Tan, Minda Chen
This patchset needs to apply after patchset in [1]. These PCIe series patches
are based on the JH7110 RISC-V SoC and VisionFive V2 board.
The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.
The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.
Mason Huo (4):
starfive: pci: Add StarFive JH7110 pcie driver
clk: starfive: Add PCIe clocks for PCIe controller
configs: starfive-jh7110: Add support for PCIe host driver
riscv: dts: starfive: Enable PCIe host controller
The JH7110 minimal system patchset upstream is in progress.
PCIe driver patches is based on this patchset.
The JH7110 minimal system patchset details are listed in [1].
[1] https://patchwork.ozlabs.org/project/uboot/cover/20230118081132.31403-1-yanhong.wang@starfivetech.com/
For more JH7110 and visionFive v2 information and support,
you can visit RVspace wiki[2].
[2] https://wiki.rvspace.org/
arch/riscv/dts/jh7110.dtsi | 79 ++++
arch/riscv/dts/starfive_visionfive2.dts | 104 +++++
configs/starfive_visionfive2_defconfig | 9 +
drivers/clk/starfive/clk-jh7110.c | 27 ++
drivers/pci/Kconfig | 11 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_starfive_jh7110.c | 482 ++++++++++++++++++++++++
7 files changed, 713 insertions(+)
create mode 100644 drivers/pci/pcie_starfive_jh7110.c
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/4] starfive: pci: Add StarFive JH7110 pcie driver
2023-02-23 10:52 [PATCH 0/4] Add StarFive JH7110 PCIe drvier support Minda Chen
@ 2023-02-23 10:52 ` Minda Chen
2023-02-23 10:52 ` [PATCH 2/4] clk: starfive: Add PCIe clocks for PCIe controller Minda Chen
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Minda Chen @ 2023-02-23 10:52 UTC (permalink / raw)
To: Simon Glass, Stefan Roese, Andrew Scull, Pali Rohár
Cc: u-boot, Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Mason Huo,
Yanhong Wang, Leyfoon Tan, Minda Chen
From: Mason Huo <mason.huo@starfivetech.com>
Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.
Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/pci/Kconfig | 11 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_starfive_jh7110.c | 482 +++++++++++++++++++++++++++++
3 files changed, 494 insertions(+)
create mode 100644 drivers/pci/pcie_starfive_jh7110.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index a3b662fb13..da9290204b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -365,4 +365,15 @@ config PCIE_UNIPHIER
Say Y here if you want to enable PCIe controller support on
UniPhier SoCs.
+config PCIE_STARFIVE_JH7110
+ bool "Enable Starfive JH7110 PCIe driver"
+ depends on STARFIVE_JH7110
+ depends on PINCTRL_STARFIVE_JH7110
+ depends on CLK_JH7110
+ depends on RESET_JH7110
+ default y
+ help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index dd1ad91ced..92a92409ab 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 0000000000..1f14352dfb
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo <mason.huo@starfivetech.com>
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <pci.h>
+#include <power-domain.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS 0x80
+#define PCIE_PCI_IDS 0x9C
+#define PCIE_WINROM 0xFC
+#define PMSG_SUPPORT_RX 0x3F0
+#define PCI_MISC 0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_REVISION_ID 0x02
+#define IDS_PCI_TO_PCI_BRIDGE 0x060400
+#define IDS_CLASS_CODE_SHIFT 8
+
+#define PREF_MEM_WIN_64_SUPPORT BIT(3)
+#define PMSG_LTR_SUPPORT BIT(2)
+#define PLDA_FUNCTION_DIS BIT(15)
+#define PLDA_FUNC_NUM 4
+#define PLDA_PHY_FUNC_SHIFT 9
+
+#define XR3PCI_ATR_AXI4_SLV0 0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
+#define XR3PCI_ATR_TRSL_PARAM 0x10
+#define XR3PCI_ATR_TABLE_OFFSET 0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM 8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
+#define XR3PCI_ATR_SRC_ADDR_MASK 0xfffff000
+#define XR3PCI_ATR_TRSL_ADDR_MASK 0xfffff000
+#define XR3_PCI_ECAM_SIZE 28
+#define XR3PCI_ATR_TRSL_DIR BIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
+
+#define ECAM_BUS_SHIFT 20
+#define ECAM_DEV_SHIFT 15
+#define ECAM_FUNC_SHIFT 12
+/* Secondary bus number offset in config space */
+#define PCI_SECONDARY_BUS 0x19
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_SHIFT 8
+#define STG_SYSCON_K_RP_NEP_MASK 0x100
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK 0x7FFF00
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK 0x7FFF
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT 0
+#define STG_SYSCON_CLKREQ_SHIFT 22
+#define STG_SYSCON_CLKREQ_MASK 0x400000
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK 0xC0000
+
+struct starfive_pcie {
+ struct udevice *dev;
+
+ void __iomem *reg_base;
+ void __iomem *cfg_base;
+
+ struct regmap *regmap;
+ u32 stg_arfun;
+ u32 stg_awfun;
+ u32 stg_rp_nep;
+
+ struct clk_bulk clks;
+ struct reset_ctl_bulk rsts;
+
+ int atr_table_num;
+ int first_busno;
+};
+
+static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
+{
+ if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+ return 0;
+ if ((PCI_BUS(bdf) == first_busno + 1) && (PCI_DEV(bdf) > 0))
+ return 0;
+
+ return 1;
+}
+
+static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset)
+{
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ unsigned int func = PCI_FUNC(bdf);
+
+ return (bus << ECAM_BUS_SHIFT) | (dev << ECAM_DEV_SHIFT) |
+ (func << ECAM_FUNC_SHIFT) | offset;
+}
+
+static bool starfive_pcie_hide_rc_bar(pci_dev_t bdf, int offset)
+{
+ /* Only root port 1 is in use */
+ if ((PCI_BUS(bdf) == 0) &&
+ (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
+ return true;
+
+ return false;
+}
+
+static int starfive_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, void **paddr)
+{
+ struct starfive_pcie *priv = dev_get_priv(udev);
+ int where = starfive_pcie_off_conf(bdf, offset);
+
+ if (!starfive_pcie_addr_valid(bdf, priv->first_busno))
+ return -EINVAL;
+
+ *paddr = (void *)(priv->cfg_base + where);
+ return 0;
+}
+
+static int starfive_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ /* Make sure the LAST TLP is finished, before reading vendor ID. */
+ if (offset == PCI_VENDOR_ID)
+ mdelay(20);
+
+ return pci_generic_mmap_read_config(udev, starfive_pcie_conf_address,
+ bdf, offset, valuep, size);
+}
+
+int starfive_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ if (starfive_pcie_hide_rc_bar(bdf, offset))
+ return 0;
+
+ return pci_generic_mmap_write_config(udev, starfive_pcie_conf_address,
+ bdf, offset, value, size);
+}
+
+static int starfive_pcie_set_atr_entry(struct starfive_pcie *priv, phys_addr_t src_addr,
+ phys_addr_t trsl_addr, size_t window_size,
+ int trsl_param)
+{
+ void __iomem *base =
+ priv->reg_base + XR3PCI_ATR_AXI4_SLV0;
+
+ /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
+ if (priv->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM) {
+ dev_err(priv->dev, "ATR table number %d exceeds max num\n",
+ priv->atr_table_num);
+ return -EINVAL;
+ }
+ base += XR3PCI_ATR_TABLE_OFFSET * priv->atr_table_num;
+ priv->atr_table_num++;
+
+ /* X3PCI_ATR_SRC_ADDR_LOW:
+ * - bit 0: enable entry,
+ * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
+ * - bits 7-11: reserved
+ * - bits 12-31: start of source address
+ */
+ writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
+ (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
+ base + XR3PCI_ATR_SRC_ADDR_LOW);
+ writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
+ writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
+ base + XR3PCI_ATR_TRSL_ADDR_LOW);
+ writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
+ writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
+
+ dev_dbg(priv->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
+ src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
+ trsl_addr, (u64)window_size, trsl_param);
+ return 0;
+}
+
+static int starfive_pcie_atr_init(struct starfive_pcie *priv)
+{
+ struct udevice *ctlr = pci_get_controller(priv->dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ int i, ret;
+
+ /* As the two host bridges in JH7110 soc have the same default
+ * address translation table, this cause the second root port can't
+ * access it's host bridge config space correctly.
+ * To workaround, config the ATR of host bridge config space by SW.
+ */
+
+ ret = starfive_pcie_set_atr_entry(priv,
+ (phys_addr_t)priv->cfg_base,
+ 0,
+ 1 << XR3_PCI_ECAM_SIZE,
+ XR3PCI_ATR_TRSLID_PCIE_CONFIG);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < hose->region_count; i++) {
+ if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
+ continue;
+
+ /* Only support identity mappings. */
+ if (hose->regions[i].bus_start !=
+ hose->regions[i].phys_start)
+ return -EINVAL;
+
+ ret = starfive_pcie_set_atr_entry(priv,
+ hose->regions[i].phys_start,
+ hose->regions[i].bus_start,
+ hose->regions[i].size,
+ XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int starfive_pcie_get_syscon(struct udevice *dev)
+{
+ struct starfive_pcie *priv = dev_get_priv(dev);
+ struct udevice *syscon;
+ struct ofnode_phandle_args syscfg_phandle;
+ u32 cells[4];
+ int ret;
+
+ /* get corresponding syscon phandle */
+ ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
+ &syscfg_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
+ &syscon);
+ if (ret) {
+ dev_err(dev, "Unable to find syscon device (%d)\n", ret);
+ return ret;
+ }
+
+ priv->regmap = syscon_get_regmap(syscon);
+ if (!priv->regmap) {
+ dev_err(dev, "Unable to find regmap\n");
+ return -ENODEV;
+ }
+
+ /* get syscon register offset */
+ ret = dev_read_u32_array(dev, "starfive,stg-syscon",
+ cells, ARRAY_SIZE(cells));
+ if (ret) {
+ dev_err(dev, "Get syscon register err %d\n", ret);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "Get syscon values: %x, %x, %x\n",
+ cells[1], cells[2], cells[3]);
+ priv->stg_arfun = cells[1];
+ priv->stg_awfun = cells[2];
+ priv->stg_rp_nep = cells[3];
+
+ return 0;
+}
+
+static int starfive_pcie_parse_dt(struct udevice *dev)
+{
+ struct starfive_pcie *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->reg_base = (void *)dev_read_addr_name(dev, "reg");
+ if (priv->reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
+ dev_err(dev, "Missing required reg address range\n");
+ return -EINVAL;
+ }
+
+ priv->cfg_base = (void *)dev_read_addr_name(dev, "config");
+ if (priv->cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
+ dev_err(dev, "Missing required config address range");
+ return -EINVAL;
+ }
+
+ ret = starfive_pcie_get_syscon(dev);
+ if (ret) {
+ dev_err(dev, "Can't get syscon: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_bulk(dev, &priv->rsts);
+ if (ret) {
+ dev_err(dev, "Can't get reset: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_get_bulk(dev, &priv->clks);
+ if (ret) {
+ dev_err(dev, "Can't get clock: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int starfive_pcie_init_port(struct udevice *dev)
+{
+ int ret, i;
+ unsigned int value;
+ struct starfive_pcie *priv = dev_get_priv(dev);
+
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret) {
+ dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_deassert_bulk(&priv->rsts);
+ if (ret) {
+ dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
+ goto err_deassert_clk;
+ }
+
+ ret = pinctrl_select_state(dev, "perst-active");
+ if (ret) {
+ dev_err(dev, "Set perst-active pinctrl failed: %d\n", ret);
+ goto err_deassert_reset;
+ }
+
+ /* Disable physical functions except #0 */
+ for (i = 1; i < PLDA_FUNC_NUM; i++) {
+ regmap_update_bits(priv->regmap,
+ priv->stg_arfun,
+ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
+ (i << PLDA_PHY_FUNC_SHIFT) <<
+ STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
+ regmap_update_bits(priv->regmap,
+ priv->stg_awfun,
+ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
+ (i << PLDA_PHY_FUNC_SHIFT) <<
+ STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
+
+ value = readl(priv->reg_base + PCI_MISC);
+ value |= PLDA_FUNCTION_DIS;
+ writel(value, priv->reg_base + PCI_MISC);
+ }
+
+ /* Disable physical functions */
+ regmap_update_bits(priv->regmap,
+ priv->stg_arfun,
+ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
+ 0 << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
+ regmap_update_bits(priv->regmap,
+ priv->stg_awfun,
+ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
+ 0 << STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
+
+ /* Enable root port */
+ value = readl(priv->reg_base + GEN_SETTINGS);
+ value |= PLDA_RP_ENABLE;
+ writel(value, priv->reg_base + GEN_SETTINGS);
+
+ /* PCIe PCI Standard Configuration Identification Settings. */
+ value = (IDS_PCI_TO_PCI_BRIDGE << IDS_CLASS_CODE_SHIFT) | IDS_REVISION_ID;
+ writel(value, priv->reg_base + PCIE_PCI_IDS);
+
+ /* The LTR message forwarding of PCIe Message Reception was set by core
+ * as default, but the forward id & addr are also need to be reset.
+ * If we do not disable LTR message forwarding here, or set a legal
+ * forwarding address, the kernel will get stuck after this driver probe.
+ * To workaround, disable the LTR message forwarding support on
+ * PCIe Message Reception.
+ */
+ value = readl(priv->reg_base + PMSG_SUPPORT_RX);
+ value &= ~PMSG_LTR_SUPPORT;
+ writel(value, priv->reg_base + PMSG_SUPPORT_RX);
+
+ /* Prefetchable memory window 64-bit addressing support */
+ value = readl(priv->reg_base + PCIE_WINROM);
+ value |= PREF_MEM_WIN_64_SUPPORT;
+ writel(value, priv->reg_base + PCIE_WINROM);
+
+ starfive_pcie_atr_init(priv);
+
+ /* Ensure that PERST has been asserted for at least 300 ms */
+ mdelay(300);
+ ret = pinctrl_select_state(dev, "perst-default");
+ if (ret) {
+ dev_err(dev, "Set perst-default pinctrl failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+
+err_deassert_clk:
+ clk_disable_bulk(&priv->clks);
+err_deassert_reset:
+ reset_assert_bulk(&priv->rsts);
+ return ret;
+}
+
+static int starfive_pcie_probe(struct udevice *dev)
+{
+ struct starfive_pcie *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->atr_table_num = 0;
+ priv->dev = dev;
+ priv->first_busno = dev_seq(dev);
+
+ ret = starfive_pcie_parse_dt(dev);
+ if (ret)
+ return ret;
+
+ regmap_update_bits(priv->regmap,
+ priv->stg_rp_nep,
+ STG_SYSCON_K_RP_NEP_MASK,
+ 1 << STG_SYSCON_K_RP_NEP_SHIFT);
+
+ regmap_update_bits(priv->regmap,
+ priv->stg_awfun,
+ STG_SYSCON_CKREF_SRC_MASK,
+ 2 << STG_SYSCON_CKREF_SRC_SHIFT);
+
+ regmap_update_bits(priv->regmap,
+ priv->stg_awfun,
+ STG_SYSCON_CLKREQ_MASK,
+ 1 << STG_SYSCON_CLKREQ_SHIFT);
+
+ ret = starfive_pcie_init_port(dev);
+ if (ret)
+ return ret;
+
+ dev_err(dev, "Starfive PCIe bus probed.\n");
+
+ return 0;
+}
+
+static const struct dm_pci_ops starfive_pcie_ops = {
+ .read_config = starfive_pcie_config_read,
+ .write_config = starfive_pcie_config_write,
+};
+
+static const struct udevice_id starfive_pcie_ids[] = {
+ { .compatible = "starfive,jh7110-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(starfive_pcie_drv) = {
+ .name = "starfive_7110_pcie",
+ .id = UCLASS_PCI,
+ .of_match = starfive_pcie_ids,
+ .ops = &starfive_pcie_ops,
+ .probe = starfive_pcie_probe,
+ .priv_auto = sizeof(struct starfive_pcie),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/4] clk: starfive: Add PCIe clocks for PCIe controller
2023-02-23 10:52 [PATCH 0/4] Add StarFive JH7110 PCIe drvier support Minda Chen
2023-02-23 10:52 ` [PATCH 1/4] starfive: pci: Add StarFive JH7110 pcie driver Minda Chen
@ 2023-02-23 10:52 ` Minda Chen
2023-02-23 10:52 ` [PATCH 3/4] configs: starfive-jh7110: Add support for PCIe host driver Minda Chen
2023-02-23 10:52 ` [PATCH 4/4] riscv: dts: starfive: Enable PCIe host controller Minda Chen
3 siblings, 0 replies; 5+ messages in thread
From: Minda Chen @ 2023-02-23 10:52 UTC (permalink / raw)
To: Simon Glass, Stefan Roese, Andrew Scull, Pali Rohár
Cc: u-boot, Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Mason Huo,
Yanhong Wang, Leyfoon Tan, Minda Chen
From: Mason Huo <mason.huo@starfivetech.com>
Add the stg clocks for StarFive JH7110 PCIe controller.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/clk/starfive/clk-jh7110.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index a904852cab..7cfed7b847 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -305,6 +305,10 @@ static int jh7110_syscrg_init(struct udevice *dev)
clk_dm(JH7110_SYSCLK_AON_APB,
starfive_clk_fix_factor(priv->reg,
"aon_apb", "apb_bus_func", 1, 1));
+ clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
+ starfive_clk_divider(priv->reg,
+ "nocstg_bus", "bus_root",
+ OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
clk_dm(JH7110_SYSCLK_QSPI_AHB,
starfive_clk_gate(priv->reg,
"qspi_ahb", "ahb1",
@@ -342,6 +346,11 @@ static int jh7110_syscrg_init(struct udevice *dev)
starfive_clk_divider(priv->reg,
"usb_125m", "gmacusb_root",
OFFSET(JH7110_SYSCLK_USB_125M), 4));
+ clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
+ starfive_clk_gate(priv->reg,
+ "noc_bus_stg_axi",
+ "nocstg_bus",
+ OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
clk_dm(JH7110_SYSCLK_GMAC1_AHB,
starfive_clk_gate(priv->reg,
"gmac1_ahb", "ahb0",
@@ -512,6 +521,24 @@ static int jh7110_stgcrg_init(struct udevice *dev)
clk_dm(JH7110_STGCLK_USB_REFCLK,
starfive_clk_divider(priv->reg, "usb_refclk", "osc",
STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
+ clk_dm(JH7110_STGCLK_PCIE0_TL,
+ starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
+ clk_dm(JH7110_STGCLK_PCIE0_AXI,
+ starfive_clk_gate(priv->reg, "pcie0_axi_mst0", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
+ clk_dm(JH7110_STGCLK_PCIE0_APB,
+ starfive_clk_gate(priv->reg, "pcie0_apb", "stg_apb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
+ clk_dm(JH7110_STGCLK_PCIE1_TL,
+ starfive_clk_gate(priv->reg, "pcie1_tl", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
+ clk_dm(JH7110_STGCLK_PCIE1_AXI,
+ starfive_clk_gate(priv->reg, "pcie1_axi_mst0", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
+ clk_dm(JH7110_STGCLK_PCIE1_APB,
+ starfive_clk_gate(priv->reg, "pcie1_apb", "stg_apb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/4] configs: starfive-jh7110: Add support for PCIe host driver
2023-02-23 10:52 [PATCH 0/4] Add StarFive JH7110 PCIe drvier support Minda Chen
2023-02-23 10:52 ` [PATCH 1/4] starfive: pci: Add StarFive JH7110 pcie driver Minda Chen
2023-02-23 10:52 ` [PATCH 2/4] clk: starfive: Add PCIe clocks for PCIe controller Minda Chen
@ 2023-02-23 10:52 ` Minda Chen
2023-02-23 10:52 ` [PATCH 4/4] riscv: dts: starfive: Enable PCIe host controller Minda Chen
3 siblings, 0 replies; 5+ messages in thread
From: Minda Chen @ 2023-02-23 10:52 UTC (permalink / raw)
To: Simon Glass, Stefan Roese, Andrew Scull, Pali Rohár
Cc: u-boot, Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Mason Huo,
Yanhong Wang, Leyfoon Tan, Minda Chen
From: Mason Huo <mason.huo@starfivetech.com>
also add the nvme driver and rtl8169 support.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
configs/starfive_visionfive2_defconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 54ae6b2a43..8e38201858 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_SYS_PCI_64BIT=y
CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
CONFIG_ARCH_RV64I=y
@@ -45,8 +46,11 @@ CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
@@ -61,6 +65,11 @@ CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_STARFIVE=y
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/4] riscv: dts: starfive: Enable PCIe host controller
2023-02-23 10:52 [PATCH 0/4] Add StarFive JH7110 PCIe drvier support Minda Chen
` (2 preceding siblings ...)
2023-02-23 10:52 ` [PATCH 3/4] configs: starfive-jh7110: Add support for PCIe host driver Minda Chen
@ 2023-02-23 10:52 ` Minda Chen
3 siblings, 0 replies; 5+ messages in thread
From: Minda Chen @ 2023-02-23 10:52 UTC (permalink / raw)
To: Simon Glass, Stefan Roese, Andrew Scull, Pali Rohár
Cc: u-boot, Lukasz Majewski, Sean Anderson, Rick Chen, Leo, Mason Huo,
Yanhong Wang, Leyfoon Tan, Minda Chen
From: Mason Huo <mason.huo@starfivetech.com>
Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
arch/riscv/dts/jh7110.dtsi | 79 ++++++++++++++++++
arch/riscv/dts/starfive_visionfive2.dts | 104 ++++++++++++++++++++++++
2 files changed, 183 insertions(+)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 49d34b85af..6f37d107e3 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -493,5 +493,84 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ pcie0: pcie@2B000000 {
+ compatible = "starfive,jh7110-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x2B000000 0x0 0x1000000>,
+ <0x9 0x40000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ msi-parent = <&plic>;
+ interrupts = <56>;
+ interrupt-controller;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE0_APB>;
+ reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+ "rst_brg", "rst_core", "rst_apb";
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ status = "disabled";
+ };
+
+ pcie1: pcie@2C000000 {
+ compatible = "starfive,jh7110-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x2C000000 0x0 0x1000000>,
+ <0x9 0xc0000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ msi-parent = <&plic>;
+ interrupts = <57>;
+ interrupt-controller;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE1_APB>;
+ reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+ "rst_brg", "rst_core", "rst_apb";
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ status = "disabled";
+ };
+
};
};
diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts
index 52b31546da..606b314bf0 100644
--- a/arch/riscv/dts/starfive_visionfive2.dts
+++ b/arch/riscv/dts/starfive_visionfive2.dts
@@ -37,6 +37,11 @@
compatible = "syscon";
reg = <0x0 0x13030000 0x0 0x1000>;
};
+
+ stg_syscon: stg_syscon@10240000 {
+ compatible = "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
};
};
@@ -189,6 +194,87 @@
slew-rate = <0>;
};
};
+
+ pcie0_perst_default: pcie0_perst_default {
+ perst-pins {
+ pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_perst_active: pcie0_perst_active {
+ perst-pins {
+ pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_wake_default: pcie0_wake_default {
+ wake-pins {
+ pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_clkreq_default: pcie0_clkreq_default {
+ clkreq-pins {
+ pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_perst_default: pcie1_perst_default {
+ perst-pins {
+ pinmux = <GPIOMUX(28, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_perst_active: pcie1_perst_active {
+ perst-pins {
+ pinmux = <GPIOMUX(28, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_wake_default: pcie1_wake_default {
+ wake-pins {
+ pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_clkreq_default: pcie1_clkreq_default {
+ clkreq-pins {
+ pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
};
&sdio0 {
@@ -229,6 +315,24 @@
};
};
+&pcie0 {
+ pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
+ pinctrl-0 = <&pcie0_perst_default>;
+ pinctrl-1 = <&pcie0_perst_active>;
+ pinctrl-2 = <&pcie0_wake_default>;
+ pinctrl-3 = <&pcie0_clkreq_default>;
+ status = "disabled";
+};
+
+&pcie1 {
+ pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
+ pinctrl-0 = <&pcie1_perst_default>;
+ pinctrl-1 = <&pcie1_perst_active>;
+ pinctrl-2 = <&pcie1_wake_default>;
+ pinctrl-3 = <&pcie1_clkreq_default>;
+ status = "okay";
+};
+
&syscrg {
starfive,sys-syscon = <&sys_syscon>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-02-23 12:59 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-02-23 10:52 [PATCH 0/4] Add StarFive JH7110 PCIe drvier support Minda Chen
2023-02-23 10:52 ` [PATCH 1/4] starfive: pci: Add StarFive JH7110 pcie driver Minda Chen
2023-02-23 10:52 ` [PATCH 2/4] clk: starfive: Add PCIe clocks for PCIe controller Minda Chen
2023-02-23 10:52 ` [PATCH 3/4] configs: starfive-jh7110: Add support for PCIe host driver Minda Chen
2023-02-23 10:52 ` [PATCH 4/4] riscv: dts: starfive: Enable PCIe host controller Minda Chen
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