From: Minda Chen <minda.chen@starfivetech.com>
To: "Simon Glass" <sjg@chromium.org>, "Stefan Roese" <sr@denx.de>,
"Andrew Scull" <ascull@google.com>,
"Pali Rohár" <pali@kernel.org>
Cc: <u-boot@lists.denx.de>, Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>, Rick Chen <rick@andestech.com>,
Leo <ycliang@andestech.com>,
Mason Huo <mason.huo@starfivetech.com>,
Yanhong Wang <yanhong.wang@starfivetech.com>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>
Subject: [PATCH 4/4] riscv: dts: starfive: Enable PCIe host controller
Date: Thu, 23 Feb 2023 18:52:40 +0800 [thread overview]
Message-ID: <20230223105240.15180-5-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230223105240.15180-1-minda.chen@starfivetech.com>
From: Mason Huo <mason.huo@starfivetech.com>
Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
arch/riscv/dts/jh7110.dtsi | 79 ++++++++++++++++++
arch/riscv/dts/starfive_visionfive2.dts | 104 ++++++++++++++++++++++++
2 files changed, 183 insertions(+)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 49d34b85af..6f37d107e3 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -493,5 +493,84 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ pcie0: pcie@2B000000 {
+ compatible = "starfive,jh7110-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x2B000000 0x0 0x1000000>,
+ <0x9 0x40000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ msi-parent = <&plic>;
+ interrupts = <56>;
+ interrupt-controller;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE0_APB>;
+ reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+ "rst_brg", "rst_core", "rst_apb";
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ status = "disabled";
+ };
+
+ pcie1: pcie@2C000000 {
+ compatible = "starfive,jh7110-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x2C000000 0x0 0x1000000>,
+ <0x9 0xc0000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ msi-parent = <&plic>;
+ interrupts = <57>;
+ interrupt-controller;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE1_APB>;
+ reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+ "rst_brg", "rst_core", "rst_apb";
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ status = "disabled";
+ };
+
};
};
diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts
index 52b31546da..606b314bf0 100644
--- a/arch/riscv/dts/starfive_visionfive2.dts
+++ b/arch/riscv/dts/starfive_visionfive2.dts
@@ -37,6 +37,11 @@
compatible = "syscon";
reg = <0x0 0x13030000 0x0 0x1000>;
};
+
+ stg_syscon: stg_syscon@10240000 {
+ compatible = "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
};
};
@@ -189,6 +194,87 @@
slew-rate = <0>;
};
};
+
+ pcie0_perst_default: pcie0_perst_default {
+ perst-pins {
+ pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_perst_active: pcie0_perst_active {
+ perst-pins {
+ pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_wake_default: pcie0_wake_default {
+ wake-pins {
+ pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_clkreq_default: pcie0_clkreq_default {
+ clkreq-pins {
+ pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_perst_default: pcie1_perst_default {
+ perst-pins {
+ pinmux = <GPIOMUX(28, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_perst_active: pcie1_perst_active {
+ perst-pins {
+ pinmux = <GPIOMUX(28, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_wake_default: pcie1_wake_default {
+ wake-pins {
+ pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_clkreq_default: pcie1_clkreq_default {
+ clkreq-pins {
+ pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
};
&sdio0 {
@@ -229,6 +315,24 @@
};
};
+&pcie0 {
+ pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
+ pinctrl-0 = <&pcie0_perst_default>;
+ pinctrl-1 = <&pcie0_perst_active>;
+ pinctrl-2 = <&pcie0_wake_default>;
+ pinctrl-3 = <&pcie0_clkreq_default>;
+ status = "disabled";
+};
+
+&pcie1 {
+ pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
+ pinctrl-0 = <&pcie1_perst_default>;
+ pinctrl-1 = <&pcie1_perst_active>;
+ pinctrl-2 = <&pcie1_wake_default>;
+ pinctrl-3 = <&pcie1_clkreq_default>;
+ status = "okay";
+};
+
&syscrg {
starfive,sys-syscon = <&sys_syscon>;
};
--
2.17.1
prev parent reply other threads:[~2023-02-23 12:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-23 10:52 [PATCH 0/4] Add StarFive JH7110 PCIe drvier support Minda Chen
2023-02-23 10:52 ` [PATCH 1/4] starfive: pci: Add StarFive JH7110 pcie driver Minda Chen
2023-02-23 10:52 ` [PATCH 2/4] clk: starfive: Add PCIe clocks for PCIe controller Minda Chen
2023-02-23 10:52 ` [PATCH 3/4] configs: starfive-jh7110: Add support for PCIe host driver Minda Chen
2023-02-23 10:52 ` Minda Chen [this message]
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