From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47A09C64ED8 for ; Sat, 25 Feb 2023 00:51:25 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 13BE885B6B; Sat, 25 Feb 2023 01:51:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A4C7985B7A; Sat, 25 Feb 2023 01:51:20 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id C6B9785B5B for ; Sat, 25 Feb 2023 01:51:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E72C61042; Fri, 24 Feb 2023 16:51:59 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B5223F881; Fri, 24 Feb 2023 16:51:15 -0800 (PST) Date: Sat, 25 Feb 2023 00:50:57 +0000 From: Andre Przywara To: qianfanguijin@163.com Cc: u-boot@lists.denx.de, Jagan Teki , Simon Glass Subject: Re: [PATCH 1/2] clk: sunxi: add THS clk/reset Message-ID: <20230225005057.19a3c38a@slackpad.lan> In-Reply-To: <20230213024256.26951-1-qianfanguijin@163.com> References: <20230213024256.26951-1-qianfanguijin@163.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Mon, 13 Feb 2023 10:42:55 +0800 qianfanguijin@163.com wrote: Hi, > From: qianfan Zhao > > Add clock/reset definitions for THS peripherals. the bits look alright, compared against the manual. But it misses the A64 clocks, the THS driver would cover that SoC, too. Cheers, Andre > Signed-off-by: qianfan Zhao > --- > drivers/clk/sunxi/clk_h3.c | 5 +++++ > drivers/clk/sunxi/clk_h6.c | 4 ++++ > drivers/clk/sunxi/clk_r40.c | 5 +++++ > 3 files changed, 14 insertions(+) > > diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c > index 213ab510ed..774d67cbfa 100644 > --- a/drivers/clk/sunxi/clk_h3.c > +++ b/drivers/clk/sunxi/clk_h3.c > @@ -38,6 +38,7 @@ static struct ccu_clk_gate h3_gates[] = { > [CLK_BUS_DE] = GATE(0x064, BIT(12)), > > [CLK_BUS_PIO] = GATE(0x068, BIT(5)), > + [CLK_BUS_THS] = GATE(0x068, BIT(8)), > > [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), > [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), > @@ -49,6 +50,8 @@ static struct ccu_clk_gate h3_gates[] = { > > [CLK_BUS_EPHY] = GATE(0x070, BIT(0)), > > + [CLK_THS] = GATE(0x074, BIT(31)), > + > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > > @@ -98,6 +101,8 @@ static struct ccu_reset h3_resets[] = { > > [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), > > + [RST_BUS_THS] = RESET(0x2d0, BIT(8)), > + > [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), > [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), > [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), > diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c > index 24eb9725db..5464530056 100644 > --- a/drivers/clk/sunxi/clk_h6.c > +++ b/drivers/clk/sunxi/clk_h6.c > @@ -42,6 +42,8 @@ static struct ccu_clk_gate h6_gates[] = { > > [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)), > > + [CLK_BUS_THS] = GATE(0x9fc, BIT(0)), > + > [CLK_USB_PHY0] = GATE(0xa70, BIT(29)), > [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)), > > @@ -91,6 +93,8 @@ static struct ccu_reset h6_resets[] = { > > [RST_BUS_EMAC] = RESET(0x97c, BIT(16)), > > + [RST_BUS_THS] = RESET(0x9fc, BIT(16)), > + > [RST_USB_PHY0] = RESET(0xa70, BIT(30)), > > [RST_USB_PHY1] = RESET(0xa74, BIT(30)), > diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c > index 630e80d2b4..4fbfd28207 100644 > --- a/drivers/clk/sunxi/clk_r40.c > +++ b/drivers/clk/sunxi/clk_r40.c > @@ -42,6 +42,7 @@ static struct ccu_clk_gate r40_gates[] = { > [CLK_BUS_TCON_TOP] = GATE(0x064, BIT(30)), > > [CLK_BUS_PIO] = GATE(0x068, BIT(5)), > + [CLK_BUS_THS] = GATE(0x068, BIT(8)), > > [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), > [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), > @@ -57,6 +58,8 @@ static struct ccu_clk_gate r40_gates[] = { > [CLK_BUS_UART6] = GATE(0x06c, BIT(22)), > [CLK_BUS_UART7] = GATE(0x06c, BIT(23)), > > + [CLK_THS] = GATE(0x074, BIT(31)), > + > [CLK_SPI0] = GATE(0x0a0, BIT(31)), > [CLK_SPI1] = GATE(0x0a4, BIT(31)), > [CLK_SPI2] = GATE(0x0a8, BIT(31)), > @@ -113,6 +116,8 @@ static struct ccu_reset r40_resets[] = { > [RST_BUS_TCON_TV1] = RESET(0x2c4, BIT(29)), > [RST_BUS_TCON_TOP] = RESET(0x2c4, BIT(30)), > > + [RST_BUS_THS] = RESET(0x2d0, BIT(8)), > + > [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), > [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), > [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),