From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84160C64EC4 for ; Sat, 4 Mar 2023 10:52:48 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A386C85DA2; Sat, 4 Mar 2023 11:51:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="B8UwkIps"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EC781859D7; Sat, 4 Mar 2023 11:51:47 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4FAC585D6B for ; Sat, 4 Mar 2023 11:51:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DD6C760B21; Sat, 4 Mar 2023 10:51:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2DE6CC433A0; Sat, 4 Mar 2023 10:51:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1677927097; bh=GgEx+I0cTnJ+GjYKc8l/JOCou8FGrUoTTEKtJollXWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B8UwkIpsO0w6Hq2GkbN98ya43FlXGvwYUFw3MCPmOt2xsc5s2/gseb4Fk2+cLvLVm aPVo4Vuo2B/Rc6B+CidlgydI5IXYIDRiUuTYxX1+bv90PuPJM9M0sXrLF5Y+wXjZ7I FlShPZ3t71Z8SPTNJtFYWYvvTdoIYL8g1Sg1TG7mGerQX1y/lWQvrgZBYSfaQrS+YM cNqse2HcRJnDJxXIqPLrPfX5VGR+R3vyowI7ohnMxnP/LxUSY4XmzoFooEqL9YQPg7 2p0wyw+OX8TSZeDkDZfbieVYapA9ZjKB+tLIBqfryv65Cj4K/C2sX04POO/F3jrbTe fpzjKQBNXd89Q== Received: by pali.im (Postfix) id 129A81262; Sat, 4 Mar 2023 11:51:35 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Martin Rowe , Tony Dinh , Stefan Roese , Chris Packham , Baruch Siach Cc: u-boot@lists.denx.de Subject: [PATCH RFC u-boot-mvebu 4/6] arm: mvebu: Define all options for A38x BOOT_FROM_* macros Date: Sat, 4 Mar 2023 11:50:34 +0100 Message-Id: <20230304105036.19189-5-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230304105036.19189-1-pali@kernel.org> References: <20230304105036.19189-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Disassembling A385 BootROM binary reveal how BootROM interprets strapping pins for Boot Device Mode. All possible options are: 0x00..0x07 -> Parallel NOR 0x08..0x15 -> Parallel NAND 0x16..0x17 -> Parallel NOR 0x18..0x25 -> Parallel NAND 0x26..0x27 -> SPI NAND 0x28..0x29 -> UART xmodem 0x2a..0x2b -> SATA 0x2c..0x2d -> PCI Express 0x2e..0x2f -> Parallel NOR 0x30..0x31 -> SD / eMMC 0x32..0x39 -> SPI NOR 0x3a..0x3c -> Parallel NOR 0x3d..0x3e -> UART debug console 0x3f -> Invalid Note that Boot Device Mode Options in A38x Hardware Specifications is incomplete. Signed-off-by: Pali Rohár --- arch/arm/mach-mvebu/include/mach/soc.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index aa42db36a1ee..698b70339436 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -160,11 +160,14 @@ #define BOOT_DEV_SEL_OFFS 4 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) -#define BOOT_FROM_NAND(x) (x == 0x0A) -#define BOOT_FROM_SATA(x) (x == 0x2A) -#define BOOT_FROM_UART(x) (x == 0x28) -#define BOOT_FROM_SPI(x) (x == 0x32) +#define BOOT_FROM_NOR(x) ((x >= 0x00 && x <= 0x07) || x == 0x16 || x == 0x17 || x == 0x2E || x == 0x2F || (x >= 0x3A && x <= 0x3C)) +#define BOOT_FROM_NAND(x) ((x >= 0x08 && x <= 0x15) || (x >= 0x18 && x <= 0x25)) +#define BOOT_FROM_SPINAND(x) (x == 0x26 || x == 0x27) +#define BOOT_FROM_UART(x) (x == 0x28 || x == 0x29) +#define BOOT_FROM_SATA(x) (x == 0x2A || x == 0x2B) +#define BOOT_FROM_PEX(x) (x == 0x2C || x == 0x2D) #define BOOT_FROM_MMC(x) (x == 0x30 || x == 0x31) +#define BOOT_FROM_SPI(x) (x >= 0x32 && x <= 0x39) #define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) -- 2.20.1