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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>, Ramon Fried <rfried.dev@gmail.com>,
	"Ariel D'Alessandro" <ariel.dalessandro@collabora.com>,
	"NXP i.MX U-Boot Team" <uboot-imx@nxp.com>,
	Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>,
	Fabio Estevam <festevam@gmail.com>,
	Joe Hershberger <joe.hershberger@ni.com>,
	Lukasz Majewski <lukma@denx.de>,
	Marcel Ziswiler <marcel.ziswiler@toradex.com>,
	Michael Trimarchi <michael@amarulasolutions.com>,
	Peng Fan <peng.fan@nxp.com>, Sean Anderson <seanga2@gmail.com>,
	Stefano Babic <sbabic@denx.de>,
	Tim Harvey <tharvey@gateworks.com>,
	Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Subject: [PATCH v4 08/14] net: dwc_eth_qos: Add i.MX8M Plus RMII support
Date: Mon,  6 Mar 2023 15:53:48 +0100	[thread overview]
Message-ID: <20230306145354.7439-8-marex@denx.de> (raw)
In-Reply-To: <20230306145354.7439-1-marex@denx.de>

With DM clock support in place, it is easy to add RMII support into the
MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.

The board DT requires the following adjustments to EQoS node:
  phy-mode = "rmii";
  assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
  			<&clk IMX8MP_SYS_PLL2_100M>,
  			<&clk IMX8MP_SYS_PLL2_50M>;
  assigned-clock-rates = <0>, <100000000>, <50000000>;

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
V2: Add RB from Ramon
V3: Handle RGMII_*ID variants
V4: No change
---
 drivers/net/dwc_eth_qos_imx.c | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index f5f3f2099f0..962c5373243 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -179,21 +179,28 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
 
 	debug("%s(dev=%p):\n", __func__, dev);
 
-	switch (eqos->phy->speed) {
-	case SPEED_1000:
-		rate = 125 * 1000 * 1000;
-		break;
-	case SPEED_100:
-		rate = 25 * 1000 * 1000;
-		break;
-	case SPEED_10:
-		rate = 2.5 * 1000 * 1000;
-		break;
-	default:
+	if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII)
+		rate = 5000;	/* 5000 kHz = 5 MHz */
+	else
+		rate = 2500;	/* 2500 kHz = 2.5 MHz */
+
+	if (eqos->phy->speed == SPEED_1000 &&
+	    (eqos->phy->interface == PHY_INTERFACE_MODE_RGMII ||
+	     eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	     eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+	     eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
+		rate *= 50;	/* Use 50x base rate i.e. 125 MHz */
+	} else if (eqos->phy->speed == SPEED_100) {
+		rate *= 10;	/* Use 10x base rate */
+	} else if (eqos->phy->speed == SPEED_10) {
+		rate *= 1;	/* Use base rate */
+	} else {
 		pr_err("invalid speed %d", eqos->phy->speed);
 		return -EINVAL;
 	}
 
+	rate *= 1000;	/* clk_set_rate() operates in Hz */
+
 	ret = clk_set_rate(&eqos->clk_tx, rate);
 	if (ret < 0) {
 		pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
-- 
2.39.2


  parent reply	other threads:[~2023-03-06 14:58 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-06 14:53 [PATCH v4 01/14] clk: imx8mp: Add EQoS MAC clock Marek Vasut
2023-03-06 14:53 ` [PATCH v4 02/14] net: Pull board_interface_eth_init() into common code Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-06 14:53 ` [PATCH v4 03/14] net: dwc_eth_qos: Drop bogus return after goto Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-06 14:53 ` [PATCH v4 04/14] net: dwc_eth_qos: Drop unused dm_gpio_free() on STM32 Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-06 14:53 ` [PATCH v4 05/14] net: dwc_eth_qos: Staticize eqos_inval_buffer_tegra186() Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-06 14:53 ` [PATCH v4 06/14] net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-06 14:53 ` [PATCH v4 07/14] net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus Marek Vasut
2023-03-30 15:31   ` sbabic
2023-03-06 14:53 ` Marek Vasut [this message]
2023-03-30 15:22   ` [PATCH v4 08/14] net: dwc_eth_qos: Add i.MX8M Plus RMII support sbabic
2023-03-06 14:53 ` [PATCH v4 09/14] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus Marek Vasut
2023-03-30 15:22   ` sbabic
2023-03-06 14:53 ` [PATCH v4 10/14] net: fec_mxc: Add ref clock setup support for i.MX8M Mini/Nano/Plus Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-06 14:53 ` [PATCH v4 11/14] net: fec_mxc: Add board_interface_eth_init() " Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-06 14:53 ` [PATCH v4 12/14] arm64: dts: imx8mp: Drop EQoS clock workaround Marek Vasut
2023-03-30 15:22   ` sbabic
2023-03-06 14:53 ` [PATCH v4 13/14] arm64: imx8mp: Drop EQoS GPR[1] board workaround Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-06 14:53 ` [PATCH v4 14/14] arm64: imx8mm: imx8mn: imx8mp: Drop FEC " Marek Vasut
2023-03-30 15:23   ` sbabic
2023-03-30 15:23 ` [PATCH v4 01/14] clk: imx8mp: Add EQoS MAC clock sbabic

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