[PATCH 0/2] Keep PLL power on

[PATCH 0/2] Keep PLL power on

[Dylan Hung]

There are several PLLs in AST2600 that provide clock sources for various
hardware blocks. According to the PLL vendor, the setting sequence was
incorrect, since the PLL power should kept on during initialization.
This patch series fixes the PLL setting sequence, including the MPLL in
the DRAM driver and the others in the clock driver.

Dylan Hung (2):
  ram: ast2600: Keep MPLL power on
  clk: ast2600: Keep PLL power on

 drivers/clk/aspeed/clk_ast2600.c   | 3 +--
 drivers/ram/aspeed/sdram_ast2600.c | 6 +++---
 2 files changed, 4 insertions(+), 5 deletions(-)

-- 
2.25.1

[PATCH 1/2] ram: ast2600: Keep MPLL power on

[Dylan Hung]

According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
---
 drivers/ram/aspeed/sdram_ast2600.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index 18767554123f..d463933363ee 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -1089,13 +1089,13 @@ static int ast2600_sdrammc_probe(struct udevice *dev)
 	}
 
 	reg = readl(&priv->scu->mpll);
-	reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK |
+	reg &= ~(SCU_PLL_BYPASS | SCU_PLL_OFF | SCU_PLL_DIV_MASK |
 		 SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK);
-	reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG);
+	reg |= (SCU_PLL_RST | SCU_MPLL_FREQ_CFG);
 	writel(reg, &priv->scu->mpll);
 	writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext);
 	udelay(100);
-	reg &= ~(SCU_PLL_RST | SCU_PLL_OFF);
+	reg &= ~SCU_PLL_RST;
 	writel(reg, &priv->scu->mpll);
 
 	while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0)
-- 
2.25.1

[PATCH 2/2] clk: ast2600: Keep PLL power on

[Dylan Hung]

According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
---
 drivers/clk/aspeed/clk_ast2600.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 0df1dc3718d3..e5ada5b6d49c 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -538,7 +538,7 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu,
 	}
 
 	p_cfg->reg.b.bypass = 0;
-	p_cfg->reg.b.off = 1;
+	p_cfg->reg.b.off = 0;
 	p_cfg->reg.b.reset = 1;
 
 	reg = readl(addr);
@@ -549,7 +549,6 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu,
 	/* write extend parameter */
 	writel(p_cfg->ext_reg, addr_ext);
 	udelay(100);
-	p_cfg->reg.b.off = 0;
 	p_cfg->reg.b.reset = 0;
 	reg &= ~GENMASK(25, 0);
 	reg |= p_cfg->reg.w;
-- 
2.25.1

Re: [PATCH 1/2] ram: ast2600: Keep MPLL power on

[Joel Stanley]

On Tue, 21 Feb 2023 at 13:01, Dylan Hung <dylan_hung@aspeedtech.com> wrote:
>
> According to the PLL vendor, we should keep the PLL power on, so we
> shouldn't toggle the power-down bit during PLL initialization.
>
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>

Reviewed-by: Joel Stanley <joel@jms.id.au>

> ---
>  drivers/ram/aspeed/sdram_ast2600.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
> index 18767554123f..d463933363ee 100644
> --- a/drivers/ram/aspeed/sdram_ast2600.c
> +++ b/drivers/ram/aspeed/sdram_ast2600.c
> @@ -1089,13 +1089,13 @@ static int ast2600_sdrammc_probe(struct udevice *dev)
>         }
>
>         reg = readl(&priv->scu->mpll);
> -       reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK |
> +       reg &= ~(SCU_PLL_BYPASS | SCU_PLL_OFF | SCU_PLL_DIV_MASK |
>                  SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK);
> -       reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG);
> +       reg |= (SCU_PLL_RST | SCU_MPLL_FREQ_CFG);
>         writel(reg, &priv->scu->mpll);
>         writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext);
>         udelay(100);
> -       reg &= ~(SCU_PLL_RST | SCU_PLL_OFF);
> +       reg &= ~SCU_PLL_RST;
>         writel(reg, &priv->scu->mpll);
>
>         while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0)
> --
> 2.25.1
>

Re: [PATCH 2/2] clk: ast2600: Keep PLL power on

[Joel Stanley]

On Tue, 21 Feb 2023 at 13:01, Dylan Hung <dylan_hung@aspeedtech.com> wrote:
>
> According to the PLL vendor, we should keep the PLL power on, so we
> shouldn't toggle the power-down bit during PLL initialization.
>
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>

Reviewed-by: Joel Stanley <joel@jms.id.au>

> ---
>  drivers/clk/aspeed/clk_ast2600.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
> index 0df1dc3718d3..e5ada5b6d49c 100644
> --- a/drivers/clk/aspeed/clk_ast2600.c
> +++ b/drivers/clk/aspeed/clk_ast2600.c
> @@ -538,7 +538,7 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu,
>         }
>
>         p_cfg->reg.b.bypass = 0;
> -       p_cfg->reg.b.off = 1;
> +       p_cfg->reg.b.off = 0;
>         p_cfg->reg.b.reset = 1;
>
>         reg = readl(addr);
> @@ -549,7 +549,6 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu,
>         /* write extend parameter */
>         writel(p_cfg->ext_reg, addr_ext);
>         udelay(100);
> -       p_cfg->reg.b.off = 0;
>         p_cfg->reg.b.reset = 0;
>         reg &= ~GENMASK(25, 0);
>         reg |= p_cfg->reg.w;
> --
> 2.25.1
>

Re: [PATCH 1/2] ram: ast2600: Keep MPLL power on

[Tom Rini]

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On Tue, Feb 21, 2023 at 09:01:09PM +0800, Dylan Hung wrote:

> According to the PLL vendor, we should keep the PLL power on, so we
> shouldn't toggle the power-down bit during PLL initialization.
> 
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
> Reviewed-by: Joel Stanley <joel@jms.id.au>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH 2/2] clk: ast2600: Keep PLL power on

[Tom Rini]

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On Tue, Feb 21, 2023 at 09:01:10PM +0800, Dylan Hung wrote:

> According to the PLL vendor, we should keep the PLL power on, so we
> shouldn't toggle the power-down bit during PLL initialization.
> 
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
> Reviewed-by: Joel Stanley <joel@jms.id.au>

Applied to u-boot/next, thanks!

-- 
Tom

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