From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18992C64EC4 for ; Thu, 9 Mar 2023 10:32:26 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9987B85B34; Thu, 9 Mar 2023 11:32:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=bootlin.com header.i=@bootlin.com header.b="CfZUI4Cs"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4129985C48; Thu, 9 Mar 2023 11:32:23 +0100 (CET) Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CEEC685A8C for ; Thu, 9 Mar 2023 11:32:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=miquel.raynal@bootlin.com Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 9F267240008; Thu, 9 Mar 2023 10:32:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1678357939; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+cXRuoz2crxClbePA4aHujvCEPsQDErwoIVjnqXYZ3c=; b=CfZUI4CsJcfRJwl5byLRWsTuib2qcfQ1YrORvwF0Al2CQtmagw8kLvsZ1CwINuX7VNHw7w sMqyDm9af0+OxDHfAhqcT5dMG6oso2lcDhkERrGB+4m5ieN9P7NfeybwFcf05BAw74CnFo HAWR/OPoDc+gCrJ95khSdDX1EjmQCbBA+THvW7PLJVpIRN2sEHVpKFGeU22fEXrPGMSmz2 htvAuphDa7vCHEhGS8pUJ8zmncPt7dBOB1vzVUdTJVxnh/b5bGzzxHrNBR3fZZuvDetyXN wdaHadDHDiZUXEvckldMV3L8mhl3RXIs0BGP3HOEYjXVr37CNAjKfqc5jc44ZA== Date: Thu, 9 Mar 2023 11:32:11 +0100 From: Miquel Raynal To: Srinivas Kandagatla Cc: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Michael Walle , gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, u-boot@lists.denx.de, =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= Subject: Re: [PATCH 2/4] nvmem: core: allow nvmem_cell_post_process_t callbacks to adjust buffer Message-ID: <20230309113211.6321ce3d@xps-13> In-Reply-To: <37f821b8-f681-08e4-d4f1-d37be191ff7f@linaro.org> References: <20230222172245.6313-1-zajec5@gmail.com> <20230222172245.6313-3-zajec5@gmail.com> <37f821b8-f681-08e4-d4f1-d37be191ff7f@linaro.org> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi Srinivas, srinivas.kandagatla@linaro.org wrote on Thu, 9 Mar 2023 10:12:24 +0000: > On 22/02/2023 17:22, Rafa=C5=82 Mi=C5=82ecki wrote: > > @@ -1791,11 +1792,15 @@ ssize_t nvmem_device_cell_read(struct nvmem_dev= ice *nvmem, > > if (!nvmem) > > return -EINVAL; =20 > > > + /* Cells with read_post_process hook may realloc buffer we can't = allow here */ =20 > > + if (info->read_post_process) > > + return -EINVAL; =20 > This should probably go in 1/4 patch. Other than that series looks good t= o me. FYI patch 1/4 is also carried by the nvmem-layouts series, so it's probably best to keep these 2 patches separated to simplify the merging. Thanks, Miqu=C3=A8l