From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5D83C7619A for ; Mon, 27 Mar 2023 08:13:49 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BCF2F86097; Mon, 27 Mar 2023 10:13:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OfGexMVA"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D95B186064; Mon, 27 Mar 2023 10:12:34 +0200 (CEST) Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 389A286061 for ; Mon, 27 Mar 2023 10:12:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=clamor95@gmail.com Received: by mail-lf1-x12e.google.com with SMTP id g17so10189774lfv.4 for ; Mon, 27 Mar 2023 01:12:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679904742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q3JO0p2Us6D/69FfE/4dqo2a/n8t2pRcJYyAopJVmWg=; b=OfGexMVAtmLKd2H7mT3yYIFDSWYzNSZKFOC04tKuh6pR5dGQjZf0Fqd3E56LNpUfra vhjsRZf/Y7voYYoRYObKhCMAkH0v/z5/DUZKQIDzGh1vb+58vjA7hBZ8uTXHK2chETWH a3vJAgTDymIV9aUtM5uXIsF2wJbDyhBV+jtKHDGdRcLCSNGAkFUZP0/r7dXzDkWRHoS2 Ic7dy2yl/U2BZF1a5QpIGLD99QOtydGv5gq1kfV4wXHCMfmixEjUw4WENkcZEjMEsHrz a9eyLB3Ola5T+4Z7pvVwpiITFLsb1gfapQRGDZ/qBNCruFb9Jiy97/NNze3x9FCR+a/S Ud8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679904742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q3JO0p2Us6D/69FfE/4dqo2a/n8t2pRcJYyAopJVmWg=; b=Tek00Am4dYZWrsidresi0ASafB/GBEevjCuj7iHkIRS7TRlBqcvzExJO8BYdlqgiRb G5DDIAKHAa0g8BDQ5su9IrkeMoDAZ8YuipOs3us00jmO1And4X/o/MgrGz/8quzsQYuF 5dcf77Fro9qT0Lf9ifD+HVLfHgIq3ytfW5L7VujT6A4SDuzg00SzIBZxzEI3lbm9vOsI aKgI7cOU51L0NPXbqG7xt0gsYO5qs4Hkelbp8SWIx8zlgDP7FIZFWqHBOK4/TfNavq2W 3PLxGGxXHnLBhZIjP7fvqDa3WNyRRQXtNWmh6nw0nzG7bh5YW2xMnjuMnZwlB1elFzP2 Iz5w== X-Gm-Message-State: AAQBX9cEEVglxUi0IZJvOaEWY9mOcHanMohrt86uEuMnWq5KQyvt5AIt zz8Z7Qp42dWwg4jDow9RUMw= X-Google-Smtp-Source: AKy350ZJX61aqJtS7omcbJx9n20oqYe/oagVfleVL8hXLBlIjwkktcZHoEMj8S47Wpn26OfeZ3HTlg== X-Received: by 2002:a05:6512:3b11:b0:4db:787:e43b with SMTP id f17-20020a0565123b1100b004db0787e43bmr5891175lfv.8.1679904742017; Mon, 27 Mar 2023 01:12:22 -0700 (PDT) Received: from xeon.. ([188.163.112.76]) by smtp.gmail.com with ESMTPSA id z2-20020a2e8402000000b002a32238ea10sm1460263ljg.53.2023.03.27.01.12.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 01:12:21 -0700 (PDT) From: Svyatoslav Ryhel To: Tom Warren , Anatolij Gustschin , Simon Glass , Svyatoslav Ryhel , Marcel Ziswiler , Thierry Reding , Maxim Schwalm , Dmitry Osipenko , Nicolas Chauvet Cc: u-boot@lists.denx.de Subject: [PATCH v3 03/11] video: tegra-dc: get clocks from device tree Date: Mon, 27 Mar 2023 11:11:42 +0300 Message-Id: <20230327081150.4585-4-clamor95@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230327081150.4585-1-clamor95@gmail.com> References: <20230327081150.4585-1-clamor95@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean DISP1 clock may use PLLP, PLLC and PLLD as parents. Instead of hardcoding, lets pass clock and its parent from device tree. Default parent is PLLP. Tested-by: Robert Eckelmann # ASUS TF101 T20 Tested-by: Nicolas Chauvet # Paz00 Tested-by: Andreas Westman Dorcsak # ASUS TF T30 Tested-by: Svyatoslav Ryhel # HTC One X T30 Signed-off-by: Svyatoslav Ryhel --- drivers/video/tegra20/tegra-dc.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index 5e3f6bf029..ff67cc8989 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -36,6 +36,7 @@ struct tegra_lcd_priv { struct disp_ctlr *disp; /* Display controller to use */ fdt_addr_t frame_buffer; /* Address of frame buffer */ unsigned pixel_clock; /* Pixel clock in Hz */ + int dc_clk[2]; /* Contains clk and its parent */ }; enum { @@ -134,7 +135,7 @@ static int update_display_mode(struct dc_disp_reg *disp, * the display clock (typically 600MHz) to the pixel clock. We round * up or down as requried. */ - rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL); + rate = clock_get_periph_rate(priv->dc_clk[0], priv->dc_clk[1]); div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2; debug("Display clock %lu, divider %lu\n", rate, div); @@ -269,20 +270,27 @@ static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv, { struct disp_ctl_win window; struct dc_ctlr *dc; + unsigned long rate = clock_get_rate(priv->dc_clk[1]); priv->frame_buffer = (u32)default_lcd_base; dc = (struct dc_ctlr *)priv->disp; /* - * A header file for clock constants was NAKed upstream. - * TODO: Put this into the FDT and fdt_lcd struct when we have clock - * support there + * We halve the rate if DISP1 paret is PLLD, since actual parent + * is plld_out0 which is PLLD divided by 2. */ - clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, - 144 * 1000000); - clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL, - 600 * 1000000); + if (priv->dc_clk[1] == CLOCK_ID_DISPLAY) + rate /= 2; + + /* + * HOST1X is init by default at 150MHz with PLLC as parent + */ + clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL, + 150 * 1000000); + clock_start_periph_pll(priv->dc_clk[0], priv->dc_clk[1], + rate); + basic_init(&dc->cmd); basic_init_timer(&dc->disp); rgb_enable(&dc->com); @@ -358,6 +366,13 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) return -EINVAL; } + ret = clock_decode_pair(dev, priv->dc_clk); + if (ret < 0) { + debug("%s: Cannot decode clocks for '%s' (ret = %d)\n", + __func__, dev->name, ret); + return -EINVAL; + } + rgb = fdt_subnode_offset(blob, node, "rgb"); if (rgb < 0) { debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n", -- 2.37.2