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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id z2-20020a2e8402000000b002a32238ea10sm1460263ljg.53.2023.03.27.01.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 01:12:22 -0700 (PDT) From: Svyatoslav Ryhel To: Tom Warren , Anatolij Gustschin , Simon Glass , Svyatoslav Ryhel , Marcel Ziswiler , Thierry Reding , Maxim Schwalm , Dmitry Osipenko , Nicolas Chauvet Cc: u-boot@lists.denx.de Subject: [PATCH v3 04/11] video: tegra-dc: request timings from panel driver first Date: Mon, 27 Mar 2023 11:11:43 +0300 Message-Id: <20230327081150.4585-5-clamor95@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230327081150.4585-1-clamor95@gmail.com> References: <20230327081150.4585-1-clamor95@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Check if panel driver has display timings and get those. If panel driver does not pass timing, try to find timing under rgb node for backwards compatibility. Tested-by: Robert Eckelmann # ASUS TF101 T20 Tested-by: Nicolas Chauvet # Paz00 Tested-by: Andreas Westman Dorcsak # ASUS TF T30 Tested-by: Svyatoslav Ryhel # LG P895 T30 Signed-off-by: Svyatoslav Ryhel --- drivers/video/tegra20/tegra-dc.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index ff67cc8989..91298b7b7f 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -380,18 +380,6 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) return -EINVAL; } - ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing); - if (ret) { - debug("%s: Cannot read display timing for '%s' (ret=%d)\n", - __func__, dev->name, ret); - return -EINVAL; - } - timing = &priv->timing; - priv->width = timing->hactive.typ; - priv->height = timing->vactive.typ; - priv->pixel_clock = timing->pixelclock.typ; - priv->log2_bpp = VIDEO_BPP16; - /* * Sadly the panel phandle is in an rgb subnode so we cannot use * uclass_get_device_by_phandle(). @@ -401,6 +389,7 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) debug("%s: Cannot find panel information\n", __func__); return -EINVAL; } + ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node, &priv->panel); if (ret) { @@ -409,6 +398,22 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) return ret; } + ret = panel_get_display_timing(priv->panel, &priv->timing); + if (ret) { + ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing); + if (ret) { + debug("%s: Cannot read display timing for '%s' (ret=%d)\n", + __func__, dev->name, ret); + return -EINVAL; + } + } + + timing = &priv->timing; + priv->width = timing->hactive.typ; + priv->height = timing->vactive.typ; + priv->pixel_clock = timing->pixelclock.typ; + priv->log2_bpp = VIDEO_BPP16; + return 0; } -- 2.37.2