From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEB5AC74A5B for ; Wed, 29 Mar 2023 19:05:34 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7ECA68591B; Wed, 29 Mar 2023 21:05:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="SznHcJE9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C21A685D34; Wed, 29 Mar 2023 21:04:39 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3FC5E85E05 for ; Wed, 29 Mar 2023 21:04:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D30E4B8241F; Wed, 29 Mar 2023 19:04:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49C27C433EF; Wed, 29 Mar 2023 19:04:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680116670; bh=+Um8owPPk6l4MDFt/Qp420xmNtECC6nAFgwwXVsnzfM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SznHcJE9sE5Z3iaAXYwy48oqY6xU6ckRoZJaziw9IUdEUEKO7ALUXY5DfU/kOeMDV GK/jAkXI5QpKfKLjpwZ1XTIOjjLqAizguqqt/x+vSLocaPS3VbfkoF4+/ePOso9Izt EayQeJwpyqgEq8tv4hPsMOmK5BiN3pxLc3VPA5YAtqy3jXWRvPwUDxBT49xue13qQ6 ToMRafAP0yfaksceFS/g+wbVQiYN7QJW9WesIEPiqByDmSmV3tvz2dT46VlEdrdTkz 1flbTpLW7I8eLfKClIL5qA0GYOLHqoZD5gghU+QzXlCx62Z6wp3xXejebyAO73EMVT eRveY/bqoUkug== Received: by pali.im (Postfix) id B5A2BBFE; Wed, 29 Mar 2023 21:04:27 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese Cc: u-boot@lists.denx.de Subject: [PATCH v2 u-boot-mvebu 3/6] arm: mvebu: Convert BOOT_FROM_* constants to function macros Date: Wed, 29 Mar 2023 21:03:32 +0200 Message-Id: <20230329190335.9861-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230329190335.9861-1-pali@kernel.org> References: <20230304105036.19189-1-pali@kernel.org> <20230329190335.9861-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one macro. And also allows to extend other BOOT_FROM_* macros for other variants. Signed-off-by: Pali Rohár Tested-by: Tony Dinh Tested-by: Martin Rowe --- arch/arm/mach-mvebu/cpu.c | 20 ++++++++++---------- arch/arm/mach-mvebu/include/mach/soc.h | 25 ++++++++++++------------- 2 files changed, 22 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 0fcd520c1dbc..1676032682b5 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -100,27 +100,27 @@ u32 get_boot_device(void) val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */ boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); - switch (boot_device) { #ifdef BOOT_FROM_NAND - case BOOT_FROM_NAND: + if (BOOT_FROM_NAND(boot_device)) return BOOT_DEVICE_NAND; #endif #ifdef BOOT_FROM_MMC - case BOOT_FROM_MMC: - case BOOT_FROM_MMC_ALT: + if (BOOT_FROM_MMC(boot_device)) return BOOT_DEVICE_MMC1; #endif - case BOOT_FROM_UART: +#ifdef BOOT_FROM_UART + if (BOOT_FROM_UART(boot_device)) return BOOT_DEVICE_UART; +#endif #ifdef BOOT_FROM_SATA - case BOOT_FROM_SATA: + if (BOOT_FROM_SATA(boot_device)) return BOOT_DEVICE_SATA; #endif - case BOOT_FROM_SPI: +#ifdef BOOT_FROM_SPI + if (BOOT_FROM_SPI(boot_device)) return BOOT_DEVICE_SPI; - default: - return BOOT_DEVICE_BOOTROM; - }; +#endif + return BOOT_DEVICE_BOOTROM; } #if defined(CONFIG_DISPLAY_CPUINFO) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 3266749836a7..82a98cf9ff57 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -143,8 +143,8 @@ #define BOOT_DEV_SEL_OFFS 3 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) -#define BOOT_FROM_UART 0x30 -#define BOOT_FROM_SPI 0x38 +#define BOOT_FROM_UART(x) (x == 0x30) +#define BOOT_FROM_SPI(x) (x == 0x38) #define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(20)) ? \ 200000000 : 166000000) @@ -160,12 +160,11 @@ #define BOOT_DEV_SEL_OFFS 4 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) -#define BOOT_FROM_NAND 0x0A -#define BOOT_FROM_SATA 0x2A -#define BOOT_FROM_UART 0x28 -#define BOOT_FROM_SPI 0x32 -#define BOOT_FROM_MMC 0x30 -#define BOOT_FROM_MMC_ALT 0x31 +#define BOOT_FROM_NAND(x) (x == 0x0A) +#define BOOT_FROM_SATA(x) (x == 0x2A) +#define BOOT_FROM_UART(x) (x == 0x28) +#define BOOT_FROM_SPI(x) (x == 0x32) +#define BOOT_FROM_MMC(x) (x == 0x30 || x == 0x31) #define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) @@ -182,9 +181,9 @@ #define BOOT_DEV_SEL_OFFS 11 #define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS) -#define BOOT_FROM_NAND 0x1 -#define BOOT_FROM_UART 0x2 -#define BOOT_FROM_SPI 0x3 +#define BOOT_FROM_NAND(x) (x == 0x1) +#define BOOT_FROM_UART(x) (x == 0x2) +#define BOOT_FROM_SPI(x) (x == 0x3) #define CFG_SYS_TCLK 200000000 /* 200MHz */ #elif defined(CONFIG_ARMADA_XP) @@ -204,8 +203,8 @@ #define BOOT_DEV_SEL_OFFS 5 #define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS) -#define BOOT_FROM_UART 0x2 -#define BOOT_FROM_SPI 0x3 +#define BOOT_FROM_UART(x) (x == 0x2) +#define BOOT_FROM_SPI(x) (x == 0x3) #define CFG_SYS_TCLK 250000000 /* 250MHz */ #endif -- 2.20.1