From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9F5EC76196 for ; Fri, 31 Mar 2023 12:59:29 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2D80E85F88; Fri, 31 Mar 2023 14:59:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="VrzyZ9yo"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 826D685F9D; Fri, 31 Mar 2023 14:59:22 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C010E85F88 for ; Fri, 31 Mar 2023 14:59:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7D60262848; Fri, 31 Mar 2023 12:59:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BE5F7C433D2; Fri, 31 Mar 2023 12:59:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680267555; bh=qYJ9rbue4ZSbXa1Vv/5zXz3xQ7D+xbzcD0LP4G299Vs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=VrzyZ9yok5guE6a8GoBxOYUvvzO9oq5sN09qXDYqT40TdfPwy4oEHcJP0XmvxwZ7k jr5VM4c4VsS35JNLOR4k6ANSxWTWDAee6hyqHns32NUg1V3+cZS72+kUfvhmtTgC0G FIyftDsYslAwXOHTtuGzprSA4oIKH38MOBF3/LsKiNMmPZ0IMxTGybKE4ukWHrkyA7 uEjhLNHfqVhZkHgxZCJlLCQGlk9R4P7Se3pGMDaR1jeHj1/HDV7ZCaZ/fRxWZ6wVQU OYlGJWOkkCfybIxuNhzdkEyEAPi7lJvk5K7JzqtwtMqPVjOwA9g2whWjxv4qislqzR aAqDlzdQvXDAQ== Received: by pali.im (Postfix) id A614D7F3; Fri, 31 Mar 2023 14:59:12 +0200 (CEST) Date: Fri, 31 Mar 2023 14:59:12 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Minda Chen Cc: Simon Glass , Stefan Roese , Andrew Scull , Mark Kettenis , u-boot@lists.denx.de, Rick Chen , Leo , Mason Huo , Yanhong Wang , Leyfoon Tan , Kevin Xie Subject: Re: [PATCH v3 1/3] starfive: pci: Add StarFive JH7110 pcie driver Message-ID: <20230331125912.4sclo6hadin7mkkd@pali> References: <20230329100143.10724-1-minda.chen@starfivetech.com> <20230329100143.10724-2-minda.chen@starfivetech.com> <20230329172746.gjbmquqvadyxaxll@pali> <3fefac0c-52b1-f7af-d1e5-8564436be1a8@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3fefac0c-52b1-f7af-d1e5-8564436be1a8@starfivetech.com> User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Friday 31 March 2023 18:35:00 Minda Chen wrote: > On 2023/3/30 1:27, Pali Rohár wrote: > > Hello! > > > > On Wednesday 29 March 2023 18:01:41 Minda Chen wrote: > >> + /* PCIe PCI Standard Configuration Identification Settings. */ > >> + value = (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT) | IDS_REVISION_ID; > >> + writel(value, priv->reg_base + PCIE_PCI_IDS); > > > > This looks like configuration of the PCI_CLASS_REVISION read-only > > register. Is there any reason why you are removing the original > > "revision" information by hardcoded IDS_REVISION_ID constant? > > > This register is not read-only register, consist resion ID and class code. > Bit [39:32]: Revision ID > Bit [63:40]: Class code I mean that this "priv->reg_base + PCIE_PCI_IDS" read-write register configures what is visible when reading read-only standard PCI register PCI_CLASS_REVISION. PCIe Root Port is by definition of PCI-to-PCI Bridge class and therefore reading from PCI_CLASS_REVISION must return PCI_CLASS_BRIDGE_PCI_* value. This is required by PCIe spec. With above driver init code it looks like that your PCIe controller does not set correct value into PCI_CLASS_REVISION register after power-on and manually setting correct value via "priv->reg_base + PCIE_PCI_IDS" is a workaround. Hopefully it is a more clear what I mean in my previous email. Also mvebu controller has this issue and has similar workaround in pci_mvebu.c driver. > And the register reset value is zero, Our PCIe version is 2.0. So set value 2. > Maybe I will add comment to this. Well, Revision ID (low 8 bits of PCI_CLASS_REVISION) is the extension to the vendor / device id register. It is not version of PCIe standard. I would expect that this Vendor ID, Device ID and Revision ID values are not being changed by the driver as they identify PCI and PCIe devices.