From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE08FC7619A for ; Tue, 11 Apr 2023 10:15:44 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F22CF85F30; Tue, 11 Apr 2023 12:15:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4952C85F40; Tue, 11 Apr 2023 12:15:16 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id AD83D85F3D for ; Tue, 11 Apr 2023 12:15:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 36F1FD75; Tue, 11 Apr 2023 03:15:46 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 43C653F73F; Tue, 11 Apr 2023 03:15:01 -0700 (PDT) Date: Tue, 11 Apr 2023 11:14:58 +0100 From: Andre Przywara To: Jernej Skrabec Cc: jagan@amarulasolutions.com, u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: Re: [PATCH v2 09/10] sunxi: Parameterize some of H616 DDR3 timings Message-ID: <20230411111458.05c73227@donnerap.cambridge.arm.com> In-Reply-To: <20230410082119.24616-10-jernej.skrabec@gmail.com> References: <20230410082119.24616-1-jernej.skrabec@gmail.com> <20230410082119.24616-10-jernej.skrabec@gmail.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Mon, 10 Apr 2023 10:21:18 +0200 Jernej Skrabec wrote: > Currently twr2rd, trd2wr and twtp are constants, but according to > vendor driver they are calculated from other values. Do that here too, > in preparation for later introduction of new parameter. > > While at it, introduce constant for t_wr_lat, which was incorrectly > calculated from tcl before. > > Signed-off-by: Jernej Skrabec The transformations look correct, though I cannot really judge their meanings. Nevertheless: Reviewed-by: Andre Przywara Cheers, Andre > --- > arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c > index 8f508344bc17..f109e920820b 100644 > --- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c > +++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c > @@ -48,10 +48,11 @@ void mctl_set_timing_params(struct dram_para *para) > u8 tcl = 7; /* JEDEC: CL / 2 => 6 */ > u8 tcwl = 5; /* JEDEC: 8 */ > u8 t_rdata_en = 9; /* ? */ > + u8 t_wr_lat = 5; /* ? */ > > - u8 twtp = 14; /* (WL + BL / 2 + tWR) / 2 */ > - u8 twr2rd = trtp + 7; /* (WL + BL / 2 + tWTR) / 2 */ > - u8 trd2wr = 5; /* (RL + BL / 2 + 2 - WL) / 2 */ > + u8 twtp = tcl + 2 + tcwl; /* (WL + BL / 2 + tWR) / 2 */ > + u8 twr2rd = trtp + 2 + tcwl; /* (WL + BL / 2 + tWTR) / 2 */ > + u8 trd2wr = tcl + 3 - tcwl; /* (RL + BL / 2 + 2 - WL) / 2 */ > > /* set DRAM timing */ > writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, > @@ -85,7 +86,7 @@ void mctl_set_timing_params(struct dram_para *para) > clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); > > /* Configure DFI timing */ > - writel((tcl - 2) | 0x2000000 | (t_rdata_en << 16) | 0x808000, > + writel(t_wr_lat | 0x2000000 | (t_rdata_en << 16) | 0x808000, > &mctl_ctl->dfitmg0); > writel(0x100202, &mctl_ctl->dfitmg1); >