[PATCH u-boot 2/3] pci: mpc85xx: Allow 8/16-bit access to PCI config space

["Pali Rohár" <pali@kernel.org>]

This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read
and write access to PCI config space as described in more Freescale
reference manuals.

This change fixes issue that 8-bit and 16-bit write to PCI config space
caused to clear adjacent bits of 32-bit PCI register.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 drivers/pci/pci_mpc85xx.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c
index 23f14db83018..d144f2b791b8 100644
--- a/drivers/pci/pci_mpc85xx.c
+++ b/drivers/pci/pci_mpc85xx.c
@@ -25,7 +25,18 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
 	addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
 	out_be32(priv->cfg_addr, addr);
 	sync();
-	*value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
+
+	switch (size) {
+	case PCI_SIZE_8:
+		*value = in_8(priv->cfg_data + (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		*value = in_le16(priv->cfg_data + (offset & 2));
+		break;
+	case PCI_SIZE_32:
+		*value = in_le32(priv->cfg_data);
+		break;
+	}
 
 	return 0;
 }
@@ -40,7 +51,18 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
 	addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
 	out_be32(priv->cfg_addr, addr);
 	sync();
-	out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
+
+	switch (size) {
+	case PCI_SIZE_8:
+		out_8(priv->cfg_data + (offset & 3), value);
+		break;
+	case PCI_SIZE_16:
+		out_le16(priv->cfg_data + (offset & 2), value);
+		break;
+	case PCI_SIZE_32:
+		out_le32(priv->cfg_data, value);
+		break;
+	}
 	sync();
 
 	return 0;
-- 
2.20.1