From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB4FBC77B61 for ; Thu, 13 Apr 2023 20:44:16 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4A1F885CB1; Thu, 13 Apr 2023 22:44:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="VtJZ77vZ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A8DBE85CF8; Thu, 13 Apr 2023 22:44:11 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1D42785C96 for ; Thu, 13 Apr 2023 22:44:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9AD226155E; Thu, 13 Apr 2023 20:44:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6896C433EF; Thu, 13 Apr 2023 20:44:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681418645; bh=WrmC/cSJygzP62D4l4IpBRfwVUd+Rr0oA5cBhBZ44PI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VtJZ77vZDedsFFzqRA1MOdB+tIshRCQ7AO4EHL4x4gNvXnRgbkb9DSFxkiSrMQQxW V51Kf36UAsUNvzuO6XT4h0AYC46QhradZWaZDlW1chae0MO9nvTEA6S4kdrN7i3WL3 gJ/zgygxp7mH6Tdz7jieZwi57djtW9M0w9ATEi4ij8QKV/0A5x996umrKpkT2j0jiU bKonJaxuc5x+9bvqDDfCoMsrZqWlynsu+IdMX2XtfRdrpMLc8qdNGlkn3//2f8WMvY JqPMpgObIAsL6KBJU+PS9Y5fBURXxlhY73509hQytO40WIqih51zsb5XcOerN1iT7A Vbvw7YqYId8RA== Received: by pali.im (Postfix) id 83CDEE10; Thu, 13 Apr 2023 22:44:03 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Heiko Schocher Cc: u-boot@lists.denx.de Subject: [PATCH u-boot 2/3] pci: mpc85xx: Allow 8/16-bit access to PCI config space Date: Thu, 13 Apr 2023 22:41:45 +0200 Message-Id: <20230413204146.9318-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230413204146.9318-1-pali@kernel.org> References: <20230413204146.9318-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read and write access to PCI config space as described in more Freescale reference manuals. This change fixes issue that 8-bit and 16-bit write to PCI config space caused to clear adjacent bits of 32-bit PCI register. Signed-off-by: Pali Rohár --- drivers/pci/pci_mpc85xx.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index 23f14db83018..d144f2b791b8 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -25,7 +25,18 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf, addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); - *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size); + + switch (size) { + case PCI_SIZE_8: + *value = in_8(priv->cfg_data + (offset & 3)); + break; + case PCI_SIZE_16: + *value = in_le16(priv->cfg_data + (offset & 2)); + break; + case PCI_SIZE_32: + *value = in_le32(priv->cfg_data); + break; + } return 0; } @@ -40,7 +51,18 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf, addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); - out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size)); + + switch (size) { + case PCI_SIZE_8: + out_8(priv->cfg_data + (offset & 3), value); + break; + case PCI_SIZE_16: + out_le16(priv->cfg_data + (offset & 2), value); + break; + case PCI_SIZE_32: + out_le32(priv->cfg_data, value); + break; + } sync(); return 0; -- 2.20.1