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From: Ralph Siemsen <ralph.siemsen@linaro.org>
To: Marek Vasut <marek.vasut@mailbox.org>
Cc: u-boot@lists.denx.de, Andrew Davis <afd@ti.com>,
	Aswath Govindraju <a-govindraju@ti.com>,
	Bryan Brattlof <bb@ti.com>, Gowtham Tammana <g-tammana@ti.com>,
	Jagan Teki <jagan@edgeble.ai>,
	Kever Yang <kever.yang@rock-chips.com>,
	Nishanth Menon <nm@ti.com>, Suman Anna <s-anna@ti.com>,
	Vignesh Raghavendra <vigneshr@ti.com>
Subject: Re: [PATCH v4 05/10] ram: cadence: add driver for Cadence EDAC
Date: Mon, 17 Apr 2023 16:33:45 -0400	[thread overview]
Message-ID: <20230417203345.GI642444@maple.netwinder.org> (raw)
In-Reply-To: <fa436ab2-afc7-ba09-e842-890ef0aff092@mailbox.org>

On Mon, Apr 17, 2023 at 07:32:30PM +0200, Marek Vasut wrote:
>On 3/8/23 21:26, Ralph Siemsen wrote:
>
>[...]
>
>>+#define FUNCCTRL	0x00
>>+#define  FUNCCTRL_MASKSDLOFS	(0x18 << 16)
>>+#define  FUNCCTRL_DVDDQ_1_5V	(1 << 8)
>>+#define  FUNCCTRL_RESET_N	(1 << 0)
>>+#define DLLCTRL		0x04
>>+#define  DLLCTRL_ASDLLOCK	(1 << 26)
>>+#define  DLLCTRL_MFSL_500MHz	(2 << 1)
>>+#define  DLLCTRL_MDLLSTBY	(1 << 0)
>
>Use BIT() macro where applicable.

Will do.

>>+	/* DDR PHY setup */
>>+	phy_writel(DLLCTRL_MFSL_500MHz | DLLCTRL_MDLLSTBY, DLLCTRL);
>>+	phy_writel(0x00000182, ZQCALCTRL);
>>+	if (ddr_type == RZN1_DDR3_DUAL_BANK)
>>+		phy_writel(0xAB330031, ZQODTCTRL);
>>+	else if (ddr_type == RZN1_DDR3_SINGLE_BANK)
>>+		phy_writel(0xAB320051, ZQODTCTRL);
>>+	else /* DDR2 */
>>+		phy_writel(0xAB330071, ZQODTCTRL);
>>+	phy_writel(0xB545B544, RDCTRL);
>>+	phy_writel(0x000000B0, RDTMG);
>>+	phy_writel(0x020A0806, OUTCTRL);
>>+	if (ddr_type == RZN1_DDR3_DUAL_BANK)
>>+		phy_writel(0x80005556, WLCTRL1);
>>+	else
>>+		phy_writel(0x80005C5D, WLCTRL1);
>>+	phy_writel(0x00000101, FIFOINIT);
>>+	phy_writel(0x00004545, DQCALOFS1);
>
>Is there any macro which defines those magic bits in magic numbers ?
>If so, please use them.

This init sequence came from the u-boot 2017 repo published by Renesas. 
There do not appear to be any macros to help with all these magic 
numbers.

>>+	/* DDR Controller is always in ASYNC mode */
>>+	cdns_ddr_ctrl_init((void *)RZN1_DDR_BASE, 1,
>>+			   ddr_00_87_async, ddr_350_374_async,
>>+			   ddr_start_addr, CFG_SYS_SDRAM_SIZE,
>>+			   priv->enable_ecc, priv->enable_8bit);
>>+
>>+	rzn1_ddr3_single_bank((void *)RZN1_DDR_BASE);
>
>Can you obtain the DRAM base from DT ?

I'll check if it is possible.

>>+	priv->syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
>>+	if (IS_ERR(priv->syscon)) {
>>+		dev_err(dev, "No syscon node found\n");
>>+		//return PTR_ERR(priv->syscon);
>
>This shouldn't be commented out, right ?

Does indeed look like an oversight. I'll fix it up, thanks for spotting!

Ralph

  reply	other threads:[~2023-04-17 20:33 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-08 20:26 [PATCH v4 00/10] Renesas RZ/N1 SoC initial support Ralph Siemsen
2023-03-08 20:26 ` [PATCH v4 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN Ralph Siemsen
2023-04-17 17:04   ` Marek Vasut
2023-04-17 18:26     ` Ralph Siemsen
2023-04-17 20:21       ` Marek Vasut
2023-04-18 14:32         ` Ralph Siemsen
2023-04-18 19:35           ` Marek Vasut
2023-03-08 20:26 ` [PATCH v4 02/10] clk: renesas: prepare for non-RCAR clock drivers Ralph Siemsen
2023-04-17 17:02   ` Marek Vasut
2023-04-17 18:22     ` Ralph Siemsen
2023-04-17 20:33       ` Marek Vasut
2023-04-17 20:48         ` Ralph Siemsen
2023-04-17 22:24           ` Marek Vasut
2023-03-08 20:26 ` [PATCH v4 03/10] clk: renesas: add R906G032 driver Ralph Siemsen
2023-04-17 17:07   ` Marek Vasut
2023-04-17 18:29     ` Ralph Siemsen
2023-03-08 20:26 ` [PATCH v4 04/10] pinctrl: " Ralph Siemsen
2023-04-17 17:09   ` Marek Vasut
2023-03-08 20:26 ` [PATCH v4 05/10] ram: cadence: add driver for Cadence EDAC Ralph Siemsen
2023-04-17 17:32   ` Marek Vasut
2023-04-17 20:33     ` Ralph Siemsen [this message]
2023-03-08 20:26 ` [PATCH v4 06/10] dts: basic devicetree for Renesas RZ/N1 SoC Ralph Siemsen
2023-04-17 17:12   ` Marek Vasut
2023-04-17 18:33     ` Ralph Siemsen
2023-04-17 20:22       ` Marek Vasut
2023-03-08 20:26 ` [PATCH v4 07/10] ARM: rzn1: basic support " Ralph Siemsen
2023-04-17 17:15   ` Marek Vasut
2023-04-17 18:57     ` Ralph Siemsen
2023-04-17 20:30       ` Marek Vasut
2023-04-17 20:44         ` Ralph Siemsen
2023-04-17 22:23           ` Marek Vasut
2023-03-08 20:26 ` [PATCH v4 08/10] board: schneider: add RZN1 board support Ralph Siemsen
2023-04-17 17:18   ` Marek Vasut
2023-04-17 19:45     ` Ralph Siemsen
2023-04-17 20:27       ` Marek Vasut
2023-03-08 20:26 ` [PATCH v4 09/10] tools: spkgimage: add Renesas SPKG format Ralph Siemsen
2023-04-17 17:23   ` Marek Vasut
2023-04-17 20:17     ` Ralph Siemsen
2023-04-17 20:28       ` Marek Vasut
2023-03-08 20:26 ` [PATCH v4 10/10] doc: renesas: add Renesas board docs Ralph Siemsen
2023-04-17 17:28   ` Marek Vasut
2023-04-17 20:29     ` Ralph Siemsen
2023-04-17 20:34       ` Marek Vasut
2023-04-17 20:50         ` Ralph Siemsen

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