From: "Pali Rohár" <pali@kernel.org>
To: Heiko Schocher <hs@denx.de>
Cc: u-boot@lists.denx.de
Subject: [PATCH u-boot 1/3] pci: mpc85xx: Do not access PCI BARs registers of BDF address 00:00.0
Date: Thu, 20 Apr 2023 21:44:23 +0200 [thread overview]
Message-ID: <20230420194425.25224-2-pali@kernel.org> (raw)
In-Reply-To: <20230420194425.25224-1-pali@kernel.org>
At BDF address 00:00.0 is fictional device which PCI configuration header
is for configuring mpc85xx PCI controller itself. PCI config space of this
device has ATMU inbound registers on position of PCI BARs. Trying to do PCI
auto configuration of this device cause rewriting ATMU inbound registers.
To avoid it, do not allow overwriting registers at BARs positions. And
because this device does not have any PCI memory, return zeros when trying
to read PCI BARs config space registers. It signals to auto configuration
tool to not allocate any PCI memory for this device.
This information is taken from MPC8544E Reference Manual, sections
17.3.1.3, 17.3.1.1.1, 17.3.2 and 17.3.2.11. Available at NXP website:
https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf
Signed-off-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/pci_mpc85xx.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c
index 833de816c459..249cfe66466b 100644
--- a/drivers/pci/pci_mpc85xx.c
+++ b/drivers/pci/pci_mpc85xx.c
@@ -27,6 +27,13 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
return 0;
}
+ /* Skip mpc85xx PCI controller's ATMU inbound registers */
+ if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5) {
+ *value = 0;
+ return 0;
+ }
+
addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
out_be32(priv->cfg_addr, addr);
sync();
@@ -56,6 +63,11 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
if (offset > 0xff)
return 0;
+ /* Skip mpc85xx PCI controller's ATMU inbound registers */
+ if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5)
+ return 0;
+
addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
out_be32(priv->cfg_addr, addr);
sync();
--
2.20.1
next prev parent reply other threads:[~2023-04-20 19:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-20 19:44 [PATCH u-boot 0/3] pci: Do not access Freescale PCI controllers BARs registers Pali Rohár
2023-04-20 19:44 ` Pali Rohár [this message]
2023-04-21 3:55 ` [PATCH u-boot 1/3] pci: mpc85xx: Do not access PCI BARs registers of BDF address 00:00.0 Heiko Schocher
2023-05-02 16:51 ` Tom Rini
2023-04-20 19:44 ` [PATCH u-boot 2/3] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port Pali Rohár
2023-04-21 3:56 ` Heiko Schocher
2023-05-02 16:51 ` Tom Rini
2023-05-02 17:53 ` [PATCH v2 u-boot] " Pali Rohár
2023-05-04 15:52 ` Tom Rini
2023-04-20 19:44 ` [PATCH u-boot 3/3] pci: auto: Remove PCI_CLASS_PROCESSOR_POWERPC autoconfig case Pali Rohár
2023-04-21 3:56 ` Heiko Schocher
2023-05-02 16:51 ` Tom Rini
2023-04-21 3:54 ` [PATCH u-boot 0/3] pci: Do not access Freescale PCI controllers BARs registers Heiko Schocher
2023-04-29 11:06 ` Pali Rohár
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