From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9BF2C7618E for ; Thu, 20 Apr 2023 19:46:18 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F198C862CD; Thu, 20 Apr 2023 21:45:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="eABL8Byr"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 74DCF862E6; Thu, 20 Apr 2023 21:45:47 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E9522862E6 for ; Thu, 20 Apr 2023 21:45:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A2C2264B7C; Thu, 20 Apr 2023 19:45:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB88CC4339B; Thu, 20 Apr 2023 19:45:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1682019941; bh=MYqrErwLbVseKhKglerr7EaS8Bx5lGckKVK4OUron1c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eABL8ByrSiLiGJ0mpF5cBzqS9RMzzCfKXQFPFOUbFBftNP/rYaPi9hbIJ5+RZEz5Z cXz1tqhA6bdlLjePaIvaufSiiw6hUbVjZ/b9msHKdiGElcPoHCEiOSmzHTHe+GhMMZ eDwXasBruHfR0jT+QM8zelIkWNlEw3ggulqattBtIrCbgmL9RT11Uid/2pJtuyLUKO qxfkYdQ5DDY87viVZJXbbjFW4BcUEUYrmn/dzHeiMgKk5epIRsSM/monLTH3EAngPu XG1aGw6SAtSY9D+RsBlzIELyNDwOBvs9/qtD1HoUnBoOmKnX8H3WO74LG4xReBd0Cp TTCkNuQlyd0hA== Received: by pali.im (Postfix) id 615261BE4; Thu, 20 Apr 2023 21:45:38 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Heiko Schocher Cc: u-boot@lists.denx.de Subject: [PATCH u-boot 2/3] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port Date: Thu, 20 Apr 2023 21:44:24 +0200 Message-Id: <20230420194425.25224-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230420194425.25224-1-pali@kernel.org> References: <20230420194425.25224-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0. PCIe Root Port does not have any PCIe memory, so returns zero when trying to read from PCIe Root Port BAR0 and ignore any writes. Signed-off-by: Pali Rohár --- drivers/pci/pcie_fsl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 4600652f2b1b..06601840da85 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -58,6 +58,14 @@ static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } + /* Skip Freescale PCIe controller's PEXCSRBAR register */ + if (PCI_BUS(bdf) - dev_seq(bus) == 0 && + PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 && + (offset & ~3) == PCI_BASE_ADDRESS_0) { + *value = 0; + return 0; + } + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus), PCI_DEV(bdf), PCI_FUNC(bdf), offset); @@ -95,6 +103,12 @@ static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf, if (fsl_pcie_addr_valid(pcie, bdf)) return 0; + /* Skip Freescale PCIe controller's PEXCSRBAR register */ + if (PCI_BUS(bdf) - dev_seq(bus) == 0 && + PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 && + (offset & ~3) == PCI_BASE_ADDRESS_0) + return 0; + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus), PCI_DEV(bdf), PCI_FUNC(bdf), offset); -- 2.20.1