From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B524BC77B73 for ; Sun, 23 Apr 2023 10:59:15 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5BDAE85F55; Sun, 23 Apr 2023 12:59:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 1139285F9D; Sun, 23 Apr 2023 12:59:09 +0200 (CEST) Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by phobos.denx.de (Postfix) with ESMTP id CE8F985D46 for ; Sun, 23 Apr 2023 12:59:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=minda.chen@starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 54ED624DFCE; Sun, 23 Apr 2023 18:59:01 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Sun, 23 Apr 2023 18:59:01 +0800 Received: from ubuntu.localdomain (113.72.145.137) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Sun, 23 Apr 2023 18:59:00 +0800 From: Minda Chen To: Simon Glass , Stefan Roese , Andrew Scull , =?UTF-8?q?Pali=20Roh=C3=A1r?= , "Mark Kettenis" CC: , Rick Chen , Leo , Mason Huo , Leyfoon Tan , Kevin Xie , "Minda Chen" Subject: [PATCH v5 0/3] Add StarFive JH7110 PCIe drvier support Date: Sun, 23 Apr 2023 18:58:56 +0800 Message-ID: <20230423105859.125764-1-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [113.72.145.137] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This patchset needs to apply after patchset in [1]. These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 board. [1] https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yanhong.wang@starfivetech.com The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init. The PCIe dts configuation includes all these setting. The PCIe drivers codes has been tested on the VisionFive V2 boards. The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter. previous patch version v1: https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.chen@starfivetech.com/ v2: https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.chen@starfivetech.com/ v3: https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.chen@starfivetech.com/ v4: https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561-1-minda.chen@starfivetech.com/ changes v5 patch 1 1. split PLDA controller driver codes to pcie_plda_common.c 2. correct the codes of record secondary number. patch 3 1. change the pcie dtsi config. make them the same with kernel. v4 patch 1 1. Remove the IDS_REVISION_ID macros. 2. Replace sec_busno to first_busno in starfive_pcie 3. Remove starfive_pcie_off_conf function. 4. Replace "imply" to "depends on" in PCIe Kconfig. 5 .Check sec_busno in starfive_pcie_addr_valid. v3 patch 1 1. remove the read vendor ID delay 2. remove starfive_pcie_hide_rc_bar function. do not hide host bridge BAR write. 3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros. 4. Add comments for bus and address limitation reason in function starfive_pcie_addr_valid 5. Change the multiple line comments in Line 373 6. Using gpio_request_by_name to get PCIe reset gpio,and using dm_gpio_set_value set GPIO value. patch 2 1. support PCIeboth 12a and 13b vf2 board. patch 3 1. reset dts change to reset-gpio. v2 1. remove clock commit. The pcie clocks change has been includeded in [1]. 2. Using GENMASK marco1 in patch1. 3. remove the syscon dts node in patch3. The syscon dts dts node has been included in [1]. Mason Huo (3): starfive: pci: Add StarFive JH7110 pcie driver configs: starfive-jh7110: Add support for PCIe host driver riscv: dts: starfive: Enable PCIe host controller .../dts/jh7110-starfive-visionfive-2.dtsi | 11 + arch/riscv/dts/jh7110.dtsi | 88 +++++ configs/starfive_visionfive2_12a_defconfig | 10 + configs/starfive_visionfive2_13b_defconfig | 10 + drivers/pci/Kconfig | 13 + drivers/pci/Makefile | 2 + drivers/pci/pcie_plda_common.c | 116 +++++++ drivers/pci/pcie_plda_common.h | 118 +++++++ drivers/pci/pcie_starfive_jh7110.c | 317 ++++++++++++++++++ 9 files changed, 685 insertions(+) create mode 100644 drivers/pci/pcie_plda_common.c create mode 100644 drivers/pci/pcie_plda_common.h create mode 100644 drivers/pci/pcie_starfive_jh7110.c base-commit: 41a88ad529b3943b1e465846eb24fe2c29203e35 -- 2.17.1