From: sin.hui.kho@intel.com
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Tien Fong Chee <tien.fong.chee@intel.com>,
Sin Hui Kho <sin.hui.kho@intel.com>,
Simon Glass <sjg@chromium.org>, Stefan Roese <sr@denx.de>,
Dinesh Maniyam <dinesh.maniyam@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>
Subject: [PATCH v1 3/5] arm: socfpga: soc64: Add F2SDRAM sideband manager base address for SOC64
Date: Mon, 24 Apr 2023 02:11:22 +0800 [thread overview]
Message-ID: <20230423181124.28077-4-sin.hui.kho@intel.com> (raw)
In-Reply-To: <20230423181124.28077-1-sin.hui.kho@intel.com>
From: Sin Hui Kho <sin.hui.kho@intel.com>
F2SDRAM sideband manager in MPFE is used in DDR driver to configure the
data traffic path.
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index eecbb037f5..cee7d482c8 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -17,6 +17,7 @@
#else
#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
#endif
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000
#define SOCFPGA_SMMU_ADDRESS 0xfa000000
#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
--
2.25.1
next prev parent reply other threads:[~2023-04-23 18:12 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-23 18:11 [PATCH v1 0/5] Add new DDR driver support for Agilex7 sin.hui.kho
2023-04-23 18:11 ` [PATCH v1 1/5] ddr: altera: agilex7: Add SDRAM driver for AGILEX7 sin.hui.kho
2023-04-23 18:11 ` [PATCH v1 2/5] arm: socfpga: agilex7: Add boot scratch register used for DDR driver sin.hui.kho
2023-04-23 18:11 ` sin.hui.kho [this message]
2023-04-23 18:11 ` [PATCH v1 4/5] arm: socfpga: agilex7: Add DDR handoff data support for AGILEX7 sin.hui.kho
2023-04-23 18:11 ` [PATCH v1 5/5] ddr: altera: Add IOSSM mailbox support for DDR driver sin.hui.kho
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230423181124.28077-4-sin.hui.kho@intel.com \
--to=sin.hui.kho@intel.com \
--cc=dinesh.maniyam@intel.com \
--cc=jit.loon.lim@intel.com \
--cc=kok.kiang.hea@intel.com \
--cc=marex@denx.de \
--cc=simon.k.r.goldschmidt@gmail.com \
--cc=sjg@chromium.org \
--cc=sr@denx.de \
--cc=teik.heng.chong@intel.com \
--cc=tien.fong.chee@intel.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox