From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFF13C77B60 for ; Sun, 23 Apr 2023 18:12:28 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4B809860A8; Sun, 23 Apr 2023 20:11:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LyQOK8SS"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 77AB58606A; Sun, 23 Apr 2023 20:11:47 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 387A48606A for ; Sun, 23 Apr 2023 20:11:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sin.hui.kho@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682273504; x=1713809504; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VgGDfJWcwJFPOa1X9LJEviiihcrmGUxoPv5mprGac/w=; b=LyQOK8SS4PMUGK/mi1OYYJNqU+6jG57RFhKy2wuVCK4GiYFWsgnCXW0M 7VGEtfsIl027dVeIsBZvjslSyNyQU3jk2Ecwz63PBP/4rhs9kEkQSL3sq Pgx/Xc9myCONDLqkcZVjjC6xDDe/8OTj6xS4Zr3THQcSl9DY4349j1Aic pTccuqUJXG78Mn6nOdcAgat+9lkoYmbHRpJoY4H3GCwOLgEpnTIBJV+XM 8NusWT+yB416Hy8R6qE0HNly1lCM/zQSb1qOHaHQqMGyNdHSen+xkGxrX FPNsFhDh+hLCOyCMMSvxQh9+XpVXnezfzYLi4b9dIJdxW+PQFQIAqSVew Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="374248734" X-IronPort-AV: E=Sophos;i="5.99,220,1677571200"; d="scan'208";a="374248734" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2023 11:11:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="695507821" X-IronPort-AV: E=Sophos;i="5.99,220,1677571200"; d="scan'208";a="695507821" Received: from pglc00257.png.intel.com ([10.221.233.180]) by fmsmga007.fm.intel.com with ESMTP; 23 Apr 2023 11:11:40 -0700 From: sin.hui.kho@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Tien Fong Chee , Sin Hui Kho , Simon Glass , Stefan Roese , Dinesh Maniyam , Jit Loon Lim , Teik Heng , Kok Kiang Subject: [PATCH v1 3/5] arm: socfpga: soc64: Add F2SDRAM sideband manager base address for SOC64 Date: Mon, 24 Apr 2023 02:11:22 +0800 Message-Id: <20230423181124.28077-4-sin.hui.kho@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230423181124.28077-1-sin.hui.kho@intel.com> References: <20230423181124.28077-1-sin.hui.kho@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Sin Hui Kho F2SDRAM sideband manager in MPFE is used in DDR driver to configure the data traffic path. Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index eecbb037f5..cee7d482c8 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -17,6 +17,7 @@ #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 -- 2.25.1