From: sin.hui.kho@intel.com
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Tien Fong Chee <tien.fong.chee@intel.com>,
Sin Hui Kho <sin.hui.kho@intel.com>,
Simon Glass <sjg@chromium.org>, Stefan Roese <sr@denx.de>,
Dinesh Maniyam <dinesh.maniyam@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>
Subject: [PATCH v1 4/5] arm: socfpga: agilex7: Add DDR handoff data support for AGILEX7
Date: Mon, 24 Apr 2023 02:11:23 +0800 [thread overview]
Message-ID: <20230423181124.28077-5-sin.hui.kho@intel.com> (raw)
In-Reply-To: <20230423181124.28077-1-sin.hui.kho@intel.com>
From: Sin Hui Kho <sin.hui.kho@intel.com>
Add AGILEX7 supported DDR handoff data
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 11 ++++++++++-
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 4 ++++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index b0134dd9bd..bfda3c42bb 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
*
*/
@@ -27,7 +27,16 @@
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7)
#define SOC64_HANDOFF_BASE 0xFFE3F000
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7)
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x628)
+/* DDR handoff */
+#define SOC64_HANDOFF_MAGIC_DDR 0x5344524D
+#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_DDR_LEN 2
+#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0)
+#else
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#endif
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
#define SOC64_HANDOFF_BASE 0xFFE5F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index e7cb5ea89c..1abbe5a0d0 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -31,6 +31,10 @@ static enum endianness check_endianness(u32 handoff)
case SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC:
debug("%s: PHY engine handoff data\n", __func__);
return LITTLE_ENDIAN;
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7)
+ case SOC64_HANDOFF_MAGIC_DDR:
+ debug("%s: SOC64_HANDOFF_MAGIC_DDR\n", __func__);
+ return BIG_ENDIAN;
#endif
default:
debug("%s: Unknown endianness!!\n", __func__);
--
2.25.1
next prev parent reply other threads:[~2023-04-23 18:12 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-23 18:11 [PATCH v1 0/5] Add new DDR driver support for Agilex7 sin.hui.kho
2023-04-23 18:11 ` [PATCH v1 1/5] ddr: altera: agilex7: Add SDRAM driver for AGILEX7 sin.hui.kho
2023-04-23 18:11 ` [PATCH v1 2/5] arm: socfpga: agilex7: Add boot scratch register used for DDR driver sin.hui.kho
2023-04-23 18:11 ` [PATCH v1 3/5] arm: socfpga: soc64: Add F2SDRAM sideband manager base address for SOC64 sin.hui.kho
2023-04-23 18:11 ` sin.hui.kho [this message]
2023-04-23 18:11 ` [PATCH v1 5/5] ddr: altera: Add IOSSM mailbox support for DDR driver sin.hui.kho
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