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23 Apr 2023 11:11:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="695507834" X-IronPort-AV: E=Sophos;i="5.99,220,1677571200"; d="scan'208";a="695507834" Received: from pglc00257.png.intel.com ([10.221.233.180]) by fmsmga007.fm.intel.com with ESMTP; 23 Apr 2023 11:11:43 -0700 From: sin.hui.kho@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Tien Fong Chee , Sin Hui Kho , Simon Glass , Stefan Roese , Dinesh Maniyam , Jit Loon Lim , Teik Heng , Kok Kiang Subject: [PATCH v1 4/5] arm: socfpga: agilex7: Add DDR handoff data support for AGILEX7 Date: Mon, 24 Apr 2023 02:11:23 +0800 Message-Id: <20230423181124.28077-5-sin.hui.kho@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230423181124.28077-1-sin.hui.kho@intel.com> References: <20230423181124.28077-1-sin.hui.kho@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Sin Hui Kho Add AGILEX7 supported DDR handoff data Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 11 ++++++++++- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 4 ++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index b0134dd9bd..bfda3c42bb 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2021 Intel Corporation + * Copyright (C) 2016-2023 Intel Corporation * */ @@ -27,7 +27,16 @@ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7) #define SOC64_HANDOFF_BASE 0xFFE3F000 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7) +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x628) +/* DDR handoff */ +#define SOC64_HANDOFF_MAGIC_DDR 0x5344524D +#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_DDR_LEN 2 +#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0) +#else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#endif #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOC64_HANDOFF_BASE 0xFFE5F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630) diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index e7cb5ea89c..1abbe5a0d0 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -31,6 +31,10 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC: debug("%s: PHY engine handoff data\n", __func__); return LITTLE_ENDIAN; +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7) + case SOC64_HANDOFF_MAGIC_DDR: + debug("%s: SOC64_HANDOFF_MAGIC_DDR\n", __func__); + return BIG_ENDIAN; #endif default: debug("%s: Unknown endianness!!\n", __func__); -- 2.25.1