From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 169C3C77B78 for ; Tue, 2 May 2023 19:01:09 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0718684738; Tue, 2 May 2023 20:59:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.b="ZNiHrfvT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 79B0D84724; Tue, 2 May 2023 20:59:34 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvsmtp11.broadcom.com [192.19.166.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CA33784710 for ; Tue, 2 May 2023 20:59:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=william.zhang@broadcom.com Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 7B52AC004601; Tue, 2 May 2023 11:59:29 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 7B52AC004601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1683053969; bh=Gja3wYOFBXF8fUeTUHOqC8x6qFLh8/lLgNmpfWGl/UI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZNiHrfvTjomntmc+7Mqk3LypQyaFrnByjbTX+8s42Fy0jq6I+Sa4MM/K7DhdNp/Uv vCtP57NRpy2Qif/7OOsETDlTgaBS/u4WM9azTx1QhDeP8vp8Geqkg4y9U2QfKtGGvw w0wy6/StZVjHOWaw0lX5pS9z4rRM7A4xd6nBN1yc= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 78EF618041CAC6; Tue, 2 May 2023 11:59:29 -0700 (PDT) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id BE0FA101C50; Tue, 2 May 2023 11:59:22 -0700 (PDT) From: William Zhang To: anand.gore@broadcom.com, kursad.oney@broadcom.com, U-Boot Mailing List , noltari@gmail.com, philippe.reynes@softathome.com, tomer.yacoby@broadcom.com, dregan@mail.com Cc: William Zhang , joel.peshkin@broadcom.com, dan.beygelman@broadcom.com, Simon Glass , Jagan Teki , Daniel Schwierzeck Subject: [PATCH v2 6/9] spi: bcm63xx-hsspi: Fix multi-bit mode setting Date: Tue, 2 May 2023 11:58:13 -0700 Message-Id: <20230502185817.374951-7-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230502185817.374951-1-william.zhang@broadcom.com> References: <20230502185817.374951-1-william.zhang@broadcom.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues. This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width. Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver") Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com Signed-off-by: William Zhang --- Changes in v2: None drivers/spi/bcm63xx_hsspi.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 495feba02262..0d12c345b1dd 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -221,7 +221,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, size_t data_bytes = bitlen / 8; size_t step_size = HSSPI_FIFO_SIZE; uint16_t opcode = 0; - uint32_t val; + uint32_t val = SPI_PFL_MODE_FILL_MASK; const uint8_t *tx = dout; uint8_t *rx = din; @@ -240,14 +240,17 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, step_size -= HSSPI_FIFO_OP_SIZE; /* dual mode */ - if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) || - (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL)) + if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) || + (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) { opcode |= HSSPI_FIFO_OP_MBIT_MASK; - /* profile mode */ - val = SPI_PFL_MODE_FILL_MASK | - SPI_PFL_MODE_MDRDSZ_MASK | - SPI_PFL_MODE_MDWRSZ_MASK; + /* profile mode */ + if (plat->mode & SPI_RX_DUAL) + val |= SPI_PFL_MODE_MDRDSZ_MASK; + if (plat->mode & SPI_TX_DUAL) + val |= SPI_PFL_MODE_MDWRSZ_MASK; + } + if (plat->mode & SPI_3WIRE) val |= SPI_PFL_MODE_3WIRE_MASK; writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); -- 2.37.3