From: Minda Chen <minda.chen@starfivetech.com>
To: "Simon Glass" <sjg@chromium.org>, "Stefan Roese" <sr@denx.de>,
"Andrew Scull" <ascull@google.com>,
"Pali Rohár" <pali@kernel.org>,
"Mark Kettenis" <kettenis@openbsd.org>
Cc: <u-boot@lists.denx.de>, Rick Chen <rick@andestech.com>,
Leo <ycliang@andestech.com>,
Mason Huo <mason.huo@starfivetech.com>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>,
Kevin Xie <kevin.xie@starfivetech.com>,
"Minda Chen" <minda.chen@starfivetech.com>
Subject: [PATCH v6 3/3] riscv: dts: starfive: Enable PCIe host controller
Date: Tue, 9 May 2023 16:26:17 +0800 [thread overview]
Message-ID: <20230509082617.119018-4-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230509082617.119018-1-minda.chen@starfivetech.com>
From: Mason Huo <mason.huo@starfivetech.com>
Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
arch/riscv/dts/jh7110.dtsi | 74 +++++++++++++++++++
2 files changed, 85 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..12245576ac 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
#include "jh7110.dtsi"
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
serial0 = &uart0;
@@ -300,6 +301,16 @@
};
};
+&pcie0 {
+ reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+};
+
+&pcie1 {
+ reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..c7b071e743 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -569,5 +569,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ pcie0: pcie@2b000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x0 0x2b000000 0x0 0x1000000
+ 0x9 0x40000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ interrupts = <56>;
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ msi-parent = <&plic>;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+ clock-names = "noc", "tl", "axi", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE0_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE0_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+ };
+
+ pcie1: pcie@2c000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x0 0x2c000000 0x0 0x1000000
+ 0x9 0xc0000000 0x0 0x10000000>;
+ reg-names = "reg", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ interrupts = <57>;
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ <0x0 0x0 0x0 0x2 &plic 0x2>,
+ <0x0 0x0 0x0 0x3 &plic 0x3>,
+ <0x0 0x0 0x0 0x4 &plic 0x4>;
+ msi-parent = <&plic>;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+ clock-names = "noc", "tl", "axi", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE1_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE1_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+ };
};
};
--
2.17.1
next prev parent reply other threads:[~2023-05-09 8:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-09 8:26 [PATCH v6 0/3] Add StarFive JH7110 PCIe drvier support Minda Chen
2023-05-09 8:26 ` [PATCH v6 1/3] starfive: pci: Add StarFive JH7110 pcie driver Minda Chen
2023-05-09 8:26 ` [PATCH v6 2/3] configs: starfive-jh7110: Add support for PCIe host driver Minda Chen
2023-05-09 8:26 ` Minda Chen [this message]
2023-06-01 1:07 ` [PATCH v6 0/3] Add StarFive JH7110 PCIe drvier support Minda Chen
[not found] ` <SEZPR03MB8064B3AAE410B18637211327C150A@SEZPR03MB8064.apcprd03.prod.outlook.com>
2023-06-08 1:19 ` Rick Chen
2023-06-16 8:42 ` Leo Liang
2023-06-16 9:34 ` Minda Chen
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