From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A30CC77B7F for ; Tue, 16 May 2023 22:01:44 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 689338665E; Wed, 17 May 2023 00:01:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 180908665E; Wed, 17 May 2023 00:01:40 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id C65F780F6C for ; Wed, 17 May 2023 00:01:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E6AC71FB; Tue, 16 May 2023 15:02:21 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 543363F7BD; Tue, 16 May 2023 15:01:35 -0700 (PDT) Date: Tue, 16 May 2023 23:01:15 +0100 From: Andre Przywara To: Sam Edwards Cc: Samuel Holland , Jagan Teki , u-boot@lists.denx.de, Icenowy Zheng , Jernej Skrabec Subject: Re: [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support Message-ID: <20230516230115.670dc94a@slackpad.lan> In-Reply-To: References: <20221206004549.29015-1-andre.przywara@arm.com> <20221206004549.29015-14-andre.przywara@arm.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.1 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Mon, 15 May 2023 20:52:23 -0600 Sam Edwards wrote: Hi Sam, > On 12/5/22 17:45, Andre Przywara wrote: > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > > index 3763ec3d2e4..33331cda5e2 100644 > > --- a/arch/arm/mach-sunxi/board.c > > +++ b/arch/arm/mach-sunxi/board.c > > @@ -148,6 +148,10 @@ static int gpio_init(void) > > sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); > > sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); > > sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); > > +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528) > > + sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); > > + sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); > > + sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); > > #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) > > sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); > > sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); > > I'm a relative outsider to sunxi, but it does look like the NCAT2 > generation's MUX is a lot more flexible in its UART assignments: e.g. > while H3's UART1-3 only had one set of pins each UART could use, the > T113 (my target) supports anywhere from 2-6 (typically 4) different > options for each of its UARTs. It is not as simple as configuring which > UART is the serial console anymore, because different boards might wire > the console header to different pins. My particular target uses UART3 on > pins PB6/PB7, for example. Well, theoretically there are indeed quite some options, but in reality we find that most boards follow some reference design, and the *debug* UART is only ever using a very few of the possible settings. For the later (ARMv8) SoCs this is mostly UART0, but for the T113 it's apparently indeed UART3. I also changed that in the Github version, to use the very same PB6/7 UART3 mux as you. > Since this patchset is updating the PIO driver anyway, maybe it's worth > updating the (preprocessor, not runtime) logic in gpio_init to support > getting the UART TX/RX pins from Kconfig, validating that the > CONFIG_CONS_INDEX and pin selection are compatible, and setting the > correct MUX function for those pins with a value pulled from a table? Mmmh, that's an idea one could follow, as this function is indeed insane. I actually rewrote gpio_init() already, to replace the hard to read #ifdef's with actual C if statements, though that's still following the same idea as the current code. Let me have a look how this would look like. Cheers, Andre