From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70A92C77B75 for ; Fri, 19 May 2023 13:41:01 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0451386328; Fri, 19 May 2023 15:40:42 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XVN86gy6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8B5B986327; Fri, 19 May 2023 15:40:40 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4A39286131 for ; Fri, 19 May 2023 15:40:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bigunclemax@gmail.com Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-307d20548adso2178236f8f.0 for ; Fri, 19 May 2023 06:40:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684503636; x=1687095636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y8+rF/p5Jdncjufm65vWHEGLS+C/ytaDC9RSOXQj3YY=; b=XVN86gy67HoVcRBvpuLqZWNZjA0qoeGsc1plc19OUmaDbDkfIz97H+xr4reZEBCj12 PokzHuazEC6QCiGZI46+hcptobvX09pQGcfer9yoxdFD7W7w9uDhwAgceQZ9NILRaH/I gvaxtYIQ9jjvb60TnHm3E9ORj5KlcY3aS1B2iDBw3tstlcrKeLTT2gWaSvZf4m4WBaF3 R0fz+CDnjhfAAZkyj9vr9/wvPSl4aVe/MxctoNRRZOTW3nC5Vr7G9OMH5V9wtlp5X9f/ FFOfUSx62PitgyezRFVsdororOdlHsSqq9tGh9qaVbBPBtGWI0J69haBU/Vi5OVBUox/ C+Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684503636; x=1687095636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y8+rF/p5Jdncjufm65vWHEGLS+C/ytaDC9RSOXQj3YY=; b=BIVofAJc2HA5kiEUXl6+vfzeq5peOA4vRnGVTtbcSRRoATcx72Yv+fTJEjA7usMwB7 3DMiHkH14gVXqDLM020VfVyJI9s3Wa2eQAracOP2LaBMOhDuG/XoLdGTomPPbA/hDNdk w+RWBpG0oY3dpjEgsGTOo7op70GZ2ugI5SYe8ZIFTTO8DN71MYq/z0wo6On4k9l5X3sP nv15nZkgqzwBVi8n+zSuz+ocXR08O9c+pgqWNoX7XwohjHjU9EOhNosihH1HKv/WpV6G /VNimAooGEcGiulbeMgirYC2qOb9/nq6TzFa7xnYNff3MR5MDE4G7s+wlfaB0/WwD+sU +C7g== X-Gm-Message-State: AC+VfDzbvvkLM5kEmV1WxzB5hTeKHweME4U+BnwLiEXS8cX2Tj5flr98 DRNdhkguOOYWqDZIPsvxebO06NiixPk= X-Google-Smtp-Source: ACHHUZ5ZYgm4pzeYsvUicktbj4rwgRUtHboj9r3ofAcxlNjpTAnaHo/yhaOSHex344NVs25oWALOmg== X-Received: by 2002:adf:df84:0:b0:306:2dc3:8b67 with SMTP id z4-20020adfdf84000000b003062dc38b67mr1991533wrl.53.1684503636216; Fri, 19 May 2023 06:40:36 -0700 (PDT) Received: from localhost.localdomain ([176.221.215.212]) by smtp.gmail.com with ESMTPSA id l5-20020adfe585000000b002f7780eee10sm5315421wrm.59.2023.05.19.06.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 06:40:35 -0700 (PDT) From: Maxim Kiselev To: u-boot@lists.denx.de Cc: Maxim Kiselev , Jagan Teki , Andre Przywara , Rick Chen , Leo Subject: [RFC PATCH v1 2/3] spi: sunxi: Add support for R329/D1/R528/T113 SPI controller Date: Fri, 19 May 2023 16:40:08 +0300 Message-Id: <20230519134010.3102343-3-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230519134010.3102343-1-bigunclemax@gmail.com> References: <20230519134010.3102343-1-bigunclemax@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean These SoCs have two SPI controllers that are quite similar to the SPI on previous Allwinner SoCs. The main difference is that new SoCs don't have a clock divider (SPI_CCR register) inside SPI IP. Instead SPI sample mode should be configured depending on the input clock. For now SPI input clock source selection is not supported by this driver, and only HOSC@24MHz can be used as input clock. Therefore, according to the, manual we could change the SPI sample mode from delay half cycle(default) to normal. This patch adds a quirk for this kind of SPI controllers Signed-off-by: Maxim Kiselev --- drivers/spi/spi-sunxi.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index c56d82d998..9ec6b359e2 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -117,6 +117,8 @@ enum sun4i_spi_bits { SPI_TCR_XCH, SPI_TCR_CS_MANUAL, SPI_TCR_CS_LEVEL, + SPI_TCR_SDC, + SPI_TCR_SDM, SPI_FCR_TF_RST, SPI_FCR_RF_RST, SPI_FSR_RF_CNT_MASK, @@ -128,6 +130,7 @@ struct sun4i_spi_variant { u32 fifo_depth; bool has_soft_reset; bool has_burst_ctl; + bool has_clk_ctl; }; struct sun4i_spi_plat { @@ -302,7 +305,19 @@ static int sun4i_spi_claim_bus(struct udevice *dev) setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) | SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW)); - sun4i_spi_set_speed_mode(dev->parent); + if (priv->variant->has_clk_ctl) { + sun4i_spi_set_speed_mode(dev->parent); + } else { + /* + * At this moment there is no ability to change input clock. + * Therefore, we can only use default HOSC@24MHz clock and + * set SPI sampling mode to normal + */ + clrsetbits_le32(SPI_REG(priv, SPI_TCR), + SPI_BIT(priv, SPI_TCR_SDC) | + SPI_BIT(priv, SPI_TCR_SDM), + SPI_BIT(priv, SPI_TCR_SDM)); + } return 0; } @@ -516,6 +531,8 @@ static const u32 sun6i_spi_bits[] = { [SPI_TCR_CS_MASK] = 0x30, [SPI_TCR_CS_MANUAL] = BIT(6), [SPI_TCR_CS_LEVEL] = BIT(7), + [SPI_TCR_SDC] = BIT(11), + [SPI_TCR_SDM] = BIT(13), [SPI_TCR_XCH] = BIT(31), [SPI_FCR_RF_RST] = BIT(15), [SPI_FCR_TF_RST] = BIT(31), @@ -526,6 +543,7 @@ static const struct sun4i_spi_variant sun4i_a10_spi_variant = { .regs = sun4i_spi_regs, .bits = sun4i_spi_bits, .fifo_depth = 64, + .has_clk_ctl = true, }; static const struct sun4i_spi_variant sun6i_a31_spi_variant = { @@ -534,6 +552,7 @@ static const struct sun4i_spi_variant sun6i_a31_spi_variant = { .fifo_depth = 128, .has_soft_reset = true, .has_burst_ctl = true, + .has_clk_ctl = true, }; static const struct sun4i_spi_variant sun8i_h3_spi_variant = { @@ -542,6 +561,15 @@ static const struct sun4i_spi_variant sun8i_h3_spi_variant = { .fifo_depth = 64, .has_soft_reset = true, .has_burst_ctl = true, + .has_clk_ctl = true, +}; + +static const struct sun4i_spi_variant sun50i_r329_spi_variant = { + .regs = sun6i_spi_regs, + .bits = sun6i_spi_bits, + .fifo_depth = 64, + .has_soft_reset = true, + .has_burst_ctl = true, }; static const struct udevice_id sun4i_spi_ids[] = { @@ -557,6 +585,10 @@ static const struct udevice_id sun4i_spi_ids[] = { .compatible = "allwinner,sun8i-h3-spi", .data = (ulong)&sun8i_h3_spi_variant, }, + { + .compatible = "allwinner,sun50i-r329-spi", + .data = (ulong)&sun50i_r329_spi_variant, + }, { /* sentinel */ } }; -- 2.39.2