Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU

Andre Przywara
2023-05-24T00:58:32Z

On Sun, 21 May 2023 21:57:57 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 12/5/22 17:45, Andre Przywara wrote:
> > From: Samuel Holland <samuel@sholland.org>
> >
> > Since the D1 CCU binding is defined, we can add support for its
> > gates/resets, following the pattern of the existing drivers.
> >
> > Signed-off-by: Samuel Holland <samuel@sholland.org>
> > Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> > Acked-by: Sean Anderson <seanga2@gmail.com>
>
> Hi Andre,
>
> So far so good! This patchset seems pretty functional. I'm still trying
> to get various peripherals on my board up and running; there are a
> couple of rough edges I'm encountering. I'll report back when I have a
> build I like.
>
> In particular, I had to update this patch in your series to be
> consistent with 46fa23f9ee. My own patch follows.

Ah, yeah, Samuel's rework. Thanks for the heads up, I somehow missed
that when updating the series!

> I'd also suggest adding to `mangopi_mq_r_defconfig`:
> CONFIG_CLK_SUN20I_D1=y
> ...or, better yet, an appropriate `select` in Kconfig?

I think this is related to the rework, I just added a "default
MACH_SUN8I_R528" line to the clock's Kconfig, similar to what we
already do for the pinctrl driver.

I merged the changes into the respective patch.

Please note that I also found a build bug for 64-bit SoCs, and that the
new DRAM driver's Kconfig symbols conflict with the already used
symbols for other DRAM drivers (like the A64 one). This broke the A64
DRAM init routine, for instance.

If the tests work well, I will try to post some proper version ASAP. If
not, I will probably just push some updated WIP version to my Github.

Thanks,
Andre

> --
>
> diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c
> index 9412b77a54..f4ff682566 100644
> --- a/drivers/clk/sunxi/clk_d1.c
> +++ b/drivers/clk/sunxi/clk_d1.c
> @@ -74,28 +74,9 @@ static struct ccu_reset d1_resets[] = {
> [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
> };
>
> -static const struct ccu_desc d1_ccu_desc = {
> +const struct ccu_desc d1_ccu_desc = {
> .gates = d1_gates,
> .resets = d1_resets,
> -};
> -
> -static int d1_clk_bind(struct udevice *dev)
> -{
> - return sunxi_reset_bind(dev, ARRAY_SIZE(d1_resets));
> -}
> -
> -static const struct udevice_id d1_ccu_ids[] = {
> - { .compatible = "allwinner,sun20i-d1-ccu",
> - .data = (ulong)&d1_ccu_desc },
> - { }
> -};
> -
> -U_BOOT_DRIVER(clk_sun20i_d1) = {
> - .name = "sun20i_d1_ccu",
> - .id = UCLASS_CLK,
> - .of_match = d1_ccu_ids,
> - .priv_auto = sizeof(struct ccu_priv),
> - .ops = &sunxi_clk_ops,
> - .probe = sunxi_clk_probe,
> - .bind = d1_clk_bind,
> + .num_gates = ARRAY_SIZE(d1_gates),
> + .num_resets = ARRAY_SIZE(d1_resets),
> };
> diff --git a/drivers/clk/sunxi/clk_sunxi.c
> b/drivers/clk/sunxi/clk_sunxi.c index ec02a2d037..176d3cbc28 100644
> --- a/drivers/clk/sunxi/clk_sunxi.c
> +++ b/drivers/clk/sunxi/clk_sunxi.c
> @@ -125,6 +125,7 @@ extern const struct ccu_desc h616_ccu_desc;
> extern const struct ccu_desc h6_r_ccu_desc;
> extern const struct ccu_desc r40_ccu_desc;
> extern const struct ccu_desc v3s_ccu_desc;
> +extern const struct ccu_desc d1_ccu_desc;
>
> static const struct udevice_id sunxi_clk_ids[] = {
> #ifdef CONFIG_CLK_SUN4I_A10
> @@ -214,6 +215,10 @@ static const struct udevice_id sunxi_clk_ids[] =
> { #ifdef CONFIG_CLK_SUNIV_F1C100S
> { .compatible = "allwinner,suniv-f1c100s-ccu",
> .data = (ulong)&f1c100s_ccu_desc },
> +#endif
> +#ifdef CONFIG_CLK_SUN20I_D1
> + { .compatible = "allwinner,sun20i-d1-ccu",
> + .data = (ulong)&d1_ccu_desc },
> #endif
> { }
> };