Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support

Sam Edwards
2023-06-18T19:01:45Z

Hi Andre,

On 6/14/23 18:07, Andre Przywara wrote:
> So I finally found some time to address some issues in the series,
> especially in the first patches (pinctrl rework and preparation).
> I pushed a branch to https://github.com/apritzel/u-boot/commits/r528-rc
> I need to do more testing, most importantly regression testing on other
> SoCs, and will only be able to post something next week, I guess.
>
> If you could briefly list the things that are still missing, I could
> try to pick some low hanging fruits.

Rebasing onto this branch ended up eliminating a good chunk of my local
hack commits. I've verified that everything is still working (but have
not yet retested NAND SPL).

The remaining local changes I have are two additions to cpu_sunxi_ncat2.h:
+#define SUNXI_R_CPUCFG_BASE 0x07000400 /* for PSCI */
+#define SUNXI_RTC_BASE 0x07090000 /* for FEL */

The former can probably be brought into my PSCI series somehow (unless
we expect more chips with CPUX blocks which might move those soft entry
registers around, then it should be defined in cpu_sunxi_*.h). The
latter is to support a reimplementation of Allwinner's `efex` command
that I'm using for development (it pokes the magic number 0x5AA5A55A
into RTC's GP_DATA_REG[2] and then resets; SPL clears that magic number
and then does an early branch to BROM+0x0020 -- exactly what Allwinner's
fork does).

I've also noticed exactly(!) one formatting difference in our clk_d1.c:
- .num_gates = ARRAY_SIZE(d1_gates),
+ .num_gates = ARRAY_SIZE(d1_gates),

Up to you if you prefer to align the = or not, but it does look
inconsistent when .gates and .resets are aligned and .num_* aren't -
might be a nitpick that comes up in patch review.

> Interesting, indeed this is left at 0, which I think will result in 288
> MHz.

Correct, at least that's what I was seeing.

> What is that frequency in your case? Do you know what the BSP
> programs?

1008 MHz, both.

> Traditionally we used something conservative that works
> without cooling and with the default voltage, but I don't know that
> value for the T113s.

For what it's worth, this board has a bare T113-s3 and the current OS
does not reclock from 1008 MHz at all, and I don't know of any users of
the board having stability issues.

In my own case, it idles at that clock at around ~35°C.

> I think CLK_SUN20I_D1 should be set by default now, so can you check
> that this is fixed?

It is now gone from my defconfig and still working, so indeed this is fixed.

> Why would we need H6 PSCI support? On the ARMv8 parts we use Trusted
> Firmware-A (TF-A) to provide PSCI services, which has a much more mature
> implementation.

It's not about the H6 and more about me being unsure whether R528/T113
is the first ARMv7-based SoC to use the new CPU management registers. If
it's not, and there's another such chip supported in U-Boot that just
lacks PSCI, it would make more sense for me to land my PSCI series
independently of our work here, and then you can add the R528 case
later. It sounds like R528/T113 may be the first such chip needing this
new code, though, so this may have to wait until the R528 series lands.

> How would this conflict, exactly? I don't see any other I2C2
> definition?

Well, no, the other definitions haven't landed in U-Boot yet. But they
do exist in the kernel, datasheets, and physical chips themselves:

PB0/PB1/PB8/PB9/PE4/PE5: i2c2 defined as muxval 4
PC0/PC1/PD20/PD21/PG6/PG7/PG14/PG15: i2c2 defined as muxval 3
PE12/PE13: i2c2 defined as muxval 2

Defining i2c2=2 universally would mean that the pins for i2c2 cannot be
changed, since it would conflict with every other definition.

> And what do you need I2C2 for, exactly?

Pins PE12/PE13 host an I²C bus with the board ID EEPROM and an Ethernet
switch that should be reset (and have a few registers set to configure
proper port isolation) very shortly after power-on.

> Well, there are shortcuts. I sketched some simpler idea in the comment
> at the top of pinctrl-sunxi.c.

My shortcut for the time being will probably be, "downstream patch."

>> At this time I have no interest in upstreaming the DT.
>
> Why not?
>
>> That might change
>> in the future, but for now it's very much meant to be out-of-tree.
>
> Why is this? This only increases your update burden, and we might break
> something and not realise that, if your DT is not in the tree.
> The question to ask should be rather: why *not* to upstream the DT?
> Please keep in mind that this would block U-Boot support, since we need
> the DT approved in the kernel before we could merge it into U-Boot.

Currently, downstream is still fairly dependent on the Tina Linux
kernel, not mainline. This is a situation I'd like to change, but it's a
push for another day -- my focus right now is only on improving the
bootloader situation.

This means that there are actually two DTs: one for the kernel, using
the Tina Linux binding values, and one for U-Boot's control FDT, which
can only support U-Boot right now (and cannot yet be tested on a real
kernel). So neither DT is acceptable upstream: the former uses
incompatible values/includes, and the latter isn't meant for Linux.

Even after(/if) this situation is resolved, the unified DT will probably
remain in a state of flux for a while, until some drivers can be updated
upstream (there's a slight mess with the I²C driver that needs to be
cleaned up and we have to use GPIO-bitbanged I²C until then, for
example) so it'll take more work before we have a "final" DT. At *that*
time, upstreaming would be a good idea...

...but for now it's very much meant to be out-of-tree. :)

(I also do not work for the company that produced this board -- I'm just
a contributor to the firmware project. Whether the project would even
use the mainline version of its DT in the first place is, though likely,
ultimately not my call.)

> Cheers,
> Andre

Likewise,
Sam