* [PATCH 0/4] rockchip: rk3588: add USB 3.0 support
@ 2023-05-29 10:01 Eugen Hristev
2023-05-29 10:01 ` [PATCH 1/4] phy: rockchip: add usbdp combo phy driver Eugen Hristev
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Eugen Hristev @ 2023-05-29 10:01 UTC (permalink / raw)
To: u-boot, kever.yang, jonas, jagan; +Cc: eugen.hristev
This series adds preliminary support for USB 3.0 using the Dual Role Devices
DRD based on DWC3 controller
One controller is in host mode :
1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
+-2 Mass Storage (480 Mb/s, 100mA)
TDK LoR TF10 C900587416E2C552
The other is in gadget mode, and to test it out, I enabled rockusb
Currently it works to remotely reboot the board e.g. :
$ sudo rkdeveloptool ld
DevNo=1 Vid=0x2207,Pid=0x350b,LocationID=601 Maskrom
$ sudo rkdeveloptool rd
Reset Device OK.
=> rockusb 0 mmc 0
dwc3-generic-peripheral usb@fc000000: request 00000000edf44580 was not queued to ep1in-bulk
rockkusb set reboot flag: 0
resetting ...
For a typeC to typeC gadget connection, it only works in one orientation.
To get orientation flipping support, another patch series is required,
for the fairchild fusb driver and type C stack.
Current patch series also adds the USB-DP combo phy driver.
The DWC3 controllers each have two PHYs, one for USB 2.0 (the inno2 usb2 phy)
and the usbdp for USB 3.0 .
Eugen Hristev (2):
ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support
configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget
Frank Wang (1):
phy: rockchip: add usbdp combo phy driver
Joseph Chen (1):
ARM: dts: rockchip: rk3588: add support for USB 3.0 devices
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 197 +++++
arch/arm/dts/rk3588-u-boot.dtsi | 93 +++
arch/arm/dts/rk3588s-u-boot.dtsi | 105 +++
configs/rock5b-rk3588_defconfig | 14 +
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-usbdp.c | 880 ++++++++++++++++++++++
include/linux/usb/phy-rockchip-usbdp.h | 70 ++
8 files changed, 1367 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
create mode 100644 include/linux/usb/phy-rockchip-usbdp.h
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/4] phy: rockchip: add usbdp combo phy driver
2023-05-29 10:01 [PATCH 0/4] rockchip: rk3588: add USB 3.0 support Eugen Hristev
@ 2023-05-29 10:01 ` Eugen Hristev
2023-07-26 7:29 ` Kever Yang
2023-05-29 10:01 ` [PATCH 2/4] ARM: dts: rockchip: rk3588: add support for USB 3.0 devices Eugen Hristev
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Eugen Hristev @ 2023-05-29 10:01 UTC (permalink / raw)
To: u-boot, kever.yang, jonas, jagan; +Cc: eugen.hristev, Frank Wang
From: Frank Wang <frank.wang@rock-chips.com>
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
[eugen.hristev@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
---
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-usbdp.c | 880 ++++++++++++++++++++++
include/linux/usb/phy-rockchip-usbdp.h | 70 ++
4 files changed, 958 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
create mode 100644 include/linux/usb/phy-rockchip-usbdp.h
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index f87ca8c31060..0247d93ab401 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -41,6 +41,13 @@ config PHY_ROCKCHIP_SNPS_PCIE3
It could support PCIe Gen3 single root complex, and could
also be able splited into multiple combinations of lanes.
+config PHY_ROCKCHIP_USBDP
+ tristate "Rockchip USBDP COMBO PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Enable this to support the Rockchip USB3.0/DP
+ combo PHY with Samsung IP block.
config PHY_ROCKCHIP_TYPEC
bool "Rockchip TYPEC PHY Driver"
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 25a803a8a86f..7fdbd107976d 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
+obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
new file mode 100644
index 000000000000..baf92529348c
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USBDP Combo PHY with Samsung IP block driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+#include <dm/of.h>
+#include <dm/of_access.h>
+#include <generic-phy.h>
+#include <linux/bitfield.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/otg.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+#include <linux/usb/phy-rockchip-usbdp.h>
+
+#define BIT_WRITEABLE_SHIFT 16
+
+enum {
+ UDPHY_MODE_NONE = 0,
+ UDPHY_MODE_USB = BIT(0),
+ UDPHY_MODE_DP = BIT(1),
+ UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
+};
+
+struct udphy_grf_reg {
+ unsigned int offset;
+ unsigned int bitend;
+ unsigned int bitstart;
+ unsigned int disable;
+ unsigned int enable;
+};
+
+/**
+ * struct reg_sequence - An individual write from a sequence of writes.
+ *
+ * @reg: Register address.
+ * @def: Register value.
+ * @delay_us: Delay to be applied after the register write in microseconds
+ *
+ * Register/value pairs for sequences of writes with an optional delay in
+ * microseconds to be applied after each write.
+ */
+struct reg_sequence {
+ unsigned int reg;
+ unsigned int def;
+ unsigned int delay_us;
+};
+
+struct udphy_grf_cfg {
+ /* u2phy-grf */
+ struct udphy_grf_reg bvalid_phy_con;
+ struct udphy_grf_reg bvalid_grf_con;
+
+ /* usb-grf */
+ struct udphy_grf_reg usb3otg0_cfg;
+ struct udphy_grf_reg usb3otg1_cfg;
+
+ /* usbdpphy-grf */
+ struct udphy_grf_reg low_pwrn;
+ struct udphy_grf_reg rx_lfps;
+};
+
+struct rockchip_udphy;
+
+struct rockchip_udphy_cfg {
+ /* resets to be requested */
+ const char * const *rst_list;
+ int num_rsts;
+
+ struct udphy_grf_cfg grfcfg;
+ int (*combophy_init)(struct rockchip_udphy *udphy);
+};
+
+struct rockchip_udphy {
+ struct udevice *dev;
+ struct regmap *pma_regmap;
+ struct regmap *u2phygrf;
+ struct regmap *udphygrf;
+ struct regmap *usbgrf;
+ struct regmap *vogrf;
+
+ /* clocks and rests */
+ struct reset_ctl *rsts;
+
+ /* PHY status management */
+ bool flip;
+ bool mode_change;
+ u8 mode;
+ u8 status;
+
+ /* utilized for USB */
+ bool hs; /* flag for high-speed */
+
+ /* utilized for DP */
+ struct gpio_desc *sbu1_dc_gpio;
+ struct gpio_desc *sbu2_dc_gpio;
+ u32 lane_mux_sel[4];
+ u32 dp_lane_sel[4];
+ u32 dp_aux_dout_sel;
+ u32 dp_aux_din_sel;
+ int id;
+
+ /* PHY const config */
+ const struct rockchip_udphy_cfg *cfgs;
+};
+
+static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
+ {0x0090, 0x68}, {0x0094, 0x68},
+ {0x0128, 0x24}, {0x012c, 0x44},
+ {0x0130, 0x3f}, {0x0134, 0x44},
+ {0x015c, 0xa9}, {0x0160, 0x71},
+ {0x0164, 0x71}, {0x0168, 0xa9},
+ {0x0174, 0xa9}, {0x0178, 0x71},
+ {0x017c, 0x71}, {0x0180, 0xa9},
+ {0x018c, 0x41}, {0x0190, 0x00},
+ {0x0194, 0x05}, {0x01ac, 0x2a},
+ {0x01b0, 0x17}, {0x01b4, 0x17},
+ {0x01b8, 0x2a}, {0x01c8, 0x04},
+ {0x01cc, 0x08}, {0x01d0, 0x08},
+ {0x01d4, 0x04}, {0x01d8, 0x20},
+ {0x01dc, 0x01}, {0x01e0, 0x09},
+ {0x01e4, 0x03}, {0x01f0, 0x29},
+ {0x01f4, 0x02}, {0x01f8, 0x02},
+ {0x01fc, 0x29}, {0x0208, 0x2a},
+ {0x020c, 0x17}, {0x0210, 0x17},
+ {0x0214, 0x2a}, {0x0224, 0x20},
+ {0x03f0, 0x0d}, {0x03f4, 0x09},
+ {0x03f8, 0x09}, {0x03fc, 0x0d},
+ {0x0404, 0x0e}, {0x0408, 0x14},
+ {0x040c, 0x14}, {0x0410, 0x3b},
+ {0x0ce0, 0x68}, {0x0ce8, 0xd0},
+ {0x0cf0, 0x87}, {0x0cf8, 0x70},
+ {0x0d00, 0x70}, {0x0d08, 0xa9},
+ {0x1ce0, 0x68}, {0x1ce8, 0xd0},
+ {0x1cf0, 0x87}, {0x1cf8, 0x70},
+ {0x1d00, 0x70}, {0x1d08, 0xa9},
+ {0x0a3c, 0xd0}, {0x0a44, 0xd0},
+ {0x0a48, 0x01}, {0x0a4c, 0x0d},
+ {0x0a54, 0xe0}, {0x0a5c, 0xe0},
+ {0x0a64, 0xa8}, {0x1a3c, 0xd0},
+ {0x1a44, 0xd0}, {0x1a48, 0x01},
+ {0x1a4c, 0x0d}, {0x1a54, 0xe0},
+ {0x1a5c, 0xe0}, {0x1a64, 0xa8}
+};
+
+static const struct reg_sequence rk3588_udphy_init_sequence[] = {
+ {0x0104, 0x44}, {0x0234, 0xE8},
+ {0x0248, 0x44}, {0x028C, 0x18},
+ {0x081C, 0xE5}, {0x0878, 0x00},
+ {0x0994, 0x1C}, {0x0AF0, 0x00},
+ {0x181C, 0xE5}, {0x1878, 0x00},
+ {0x1994, 0x1C}, {0x1AF0, 0x00},
+ {0x0428, 0x60}, {0x0D58, 0x33},
+ {0x1D58, 0x33}, {0x0990, 0x74},
+ {0x0D64, 0x17}, {0x08C8, 0x13},
+ {0x1990, 0x74}, {0x1D64, 0x17},
+ {0x18C8, 0x13}, {0x0D90, 0x40},
+ {0x0DA8, 0x40}, {0x0DC0, 0x40},
+ {0x0DD8, 0x40}, {0x1D90, 0x40},
+ {0x1DA8, 0x40}, {0x1DC0, 0x40},
+ {0x1DD8, 0x40}, {0x03C0, 0x30},
+ {0x03C4, 0x06}, {0x0E10, 0x00},
+ {0x1E10, 0x00}, {0x043C, 0x0F},
+ {0x0D2C, 0xFF}, {0x1D2C, 0xFF},
+ {0x0D34, 0x0F}, {0x1D34, 0x0F},
+ {0x08FC, 0x2A}, {0x0914, 0x28},
+ {0x0A30, 0x03}, {0x0E38, 0x05},
+ {0x0ECC, 0x27}, {0x0ED0, 0x22},
+ {0x0ED4, 0x26}, {0x18FC, 0x2A},
+ {0x1914, 0x28}, {0x1A30, 0x03},
+ {0x1E38, 0x05}, {0x1ECC, 0x27},
+ {0x1ED0, 0x22}, {0x1ED4, 0x26},
+ {0x0048, 0x0F}, {0x0060, 0x3C},
+ {0x0064, 0xF7}, {0x006C, 0x20},
+ {0x0070, 0x7D}, {0x0074, 0x68},
+ {0x0AF4, 0x1A}, {0x1AF4, 0x1A},
+ {0x0440, 0x3F}, {0x10D4, 0x08},
+ {0x20D4, 0x08}, {0x00D4, 0x30},
+ {0x0024, 0x6e},
+};
+
+static inline int grfreg_write(struct regmap *base,
+ const struct udphy_grf_reg *reg, bool en)
+{
+ u32 val, mask, tmp;
+
+ tmp = en ? reg->enable : reg->disable;
+ mask = GENMASK(reg->bitend, reg->bitstart);
+ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+ return regmap_write(base, reg->offset, val);
+}
+
+static int __regmap_multi_reg_write(struct regmap *map,
+ const struct reg_sequence *regs,
+ int num_regs)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < num_regs; i++) {
+ ret = regmap_write(map, regs[i].reg, regs[i].def);
+
+ if (regs[i].delay_us)
+ udelay(regs[i].delay_us);
+ }
+
+ return ret;
+}
+
+static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev)
+{
+ return 0;
+}
+
+static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev)
+{
+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+ int idx;
+ int ret;
+
+ udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
+ sizeof(*udphy->rsts), GFP_KERNEL);
+ if (!udphy->rsts)
+ return -ENOMEM;
+
+ for (idx = 0; idx < cfg->num_rsts; idx++) {
+ const char *name = cfg->rst_list[idx];
+
+ ret = reset_get_by_name(dev, name, &udphy->rsts[idx]);
+ if (ret) {
+ dev_err(dev, "failed to get %s reset\n", name);
+ goto err;
+ }
+
+ reset_assert(&udphy->rsts[idx]);
+ }
+
+ return 0;
+
+err:
+ devm_kfree(dev, udphy->rsts);
+ return ret;
+}
+
+static int udphy_get_rst_idx(const char * const *list, int num, char *name)
+{
+ int idx;
+
+ for (idx = 0; idx < num; idx++) {
+ if (!strcmp(list[idx], name))
+ return idx;
+ }
+
+ return -EINVAL;
+}
+
+static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
+{
+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+ int idx;
+
+ idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
+ if (idx < 0)
+ return idx;
+
+ return reset_assert(&udphy->rsts[idx]);
+}
+
+static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
+{
+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+ int idx;
+
+ idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
+ if (idx < 0)
+ return idx;
+
+ return reset_deassert(&udphy->rsts[idx]);
+}
+
+static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
+{
+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+ const struct udphy_grf_reg *preg;
+
+ preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
+ grfreg_write(udphy->usbgrf, preg, disable);
+}
+
+__maybe_unused
+static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
+{
+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+
+ grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
+ grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
+}
+
+/*
+ * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
+ *
+ * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
+ * ---------------------------------------------------------------------------
+ * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
+ * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
+ * C/E(Normal) dpln3 dpln2 dpln0 dpln1
+ * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
+ * D/F(Normal) usbrx usbtx dpln0 dpln1
+ * D/F(Flip ) dpln0 dpln1 usbrx usbtx
+ * A(Normal ) dpln3 dpln1 dpln2 dpln0
+ * A(Flip ) dpln2 dpln0 dpln3 dpln1
+ * B(Normal ) usbrx usbtx dpln1 dpln0
+ * B(Flip ) dpln1 dpln0 usbrx usbtx
+ * ---------------------------------------------------------------------------
+ *
+ * 2 Mapping the lanes in dtsi
+ * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
+ * sample as follow:
+ * ---------------------------------------------------------------------------
+ * B11-B10 A2-A3 A11-A10 B2-B3
+ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
+ * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
+ * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
+ * ---------------------------------------------------------------------------
+ * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
+ * sample as follow:
+ * ---------------------------------------------------------------------------
+ * B11-B10 A2-A3 A11-A10 B2-B3
+ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
+ * <0 1> dpln0 dpln1 usbrx usbtx
+ * <2 3> usbrx usbtx dpln0 dpln1
+ * ---------------------------------------------------------------------------
+ */
+
+__maybe_unused
+static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
+{
+ if (udphy->flip) {
+ udphy->dp_lane_sel[0] = 0;
+ udphy->dp_lane_sel[1] = 1;
+ udphy->dp_lane_sel[2] = 3;
+ udphy->dp_lane_sel[3] = 2;
+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
+ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
+ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
+ } else {
+ udphy->dp_lane_sel[0] = 2;
+ udphy->dp_lane_sel[1] = 3;
+ udphy->dp_lane_sel[2] = 1;
+ udphy->dp_lane_sel[3] = 0;
+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
+ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
+ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
+ }
+
+ udphy->mode = UDPHY_MODE_DP_USB;
+
+ return 0;
+}
+
+static int udphy_setup(struct rockchip_udphy *udphy)
+{
+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+ int ret = 0;
+
+ if (cfg->combophy_init) {
+ ret = cfg->combophy_init(udphy);
+ if (ret)
+ dev_err(udphy->dev, "failed to init usbdp combophy\n");
+ }
+
+ return ret;
+}
+
+static int udphy_disable(struct rockchip_udphy *udphy)
+{
+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+ int i;
+
+ for (i = 0; i < cfg->num_rsts; i++)
+ reset_assert(&udphy->rsts[i]);
+
+ return 0;
+}
+
+static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy,
+ const struct device_node *np)
+{
+ struct property *prop;
+ int ret, i, len, num_lanes;
+
+ prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
+ if (!prop) {
+ dev_dbg(udphy->dev,
+ "failed to find dp lane mux, following dp alt mode\n");
+ udphy->mode = UDPHY_MODE_USB;
+ return 0;
+ }
+
+ num_lanes = len / sizeof(u32);
+
+ if (num_lanes != 2 && num_lanes != 4) {
+ dev_err(udphy->dev, "invalid number of lane mux\n");
+ return -EINVAL;
+ }
+
+ ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel,
+ num_lanes);
+ if (ret) {
+ dev_err(udphy->dev, "get dp lane mux failed\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_lanes; i++) {
+ int j;
+
+ if (udphy->dp_lane_sel[i] > 3) {
+ dev_err(udphy->dev,
+ "lane mux between 0 and 3, exceeding the range\n");
+ return -EINVAL;
+ }
+
+ udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
+
+ for (j = i + 1; j < num_lanes; j++) {
+ if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
+ dev_err(udphy->dev,
+ "set repeat lane mux value\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ udphy->mode = UDPHY_MODE_DP;
+ if (num_lanes == 2)
+ udphy->mode |= UDPHY_MODE_USB;
+
+ return 0;
+}
+
+static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
+{
+ const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
+ enum usb_device_speed maximum_speed;
+ int ret;
+
+ udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev,
+ "rockchip,u2phy-grf");
+ if (IS_ERR(udphy->u2phygrf)) {
+ if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
+ dev_warn(dev, "missing u2phy-grf dt node\n");
+ udphy->u2phygrf = NULL;
+ } else {
+ return PTR_ERR(udphy->u2phygrf);
+ }
+ }
+
+ udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev,
+ "rockchip,usbdpphy-grf");
+ if (IS_ERR(udphy->udphygrf)) {
+ if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
+ dev_warn(dev, "missing usbdpphy-grf dt node\n");
+ udphy->udphygrf = NULL;
+ } else {
+ return PTR_ERR(udphy->udphygrf);
+ }
+ }
+
+ udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev,
+ "rockchip,usb-grf");
+ if (IS_ERR(udphy->usbgrf)) {
+ if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
+ dev_warn(dev, "missing usb-grf dt node\n");
+ udphy->usbgrf = NULL;
+ } else {
+ return PTR_ERR(udphy->usbgrf);
+ }
+ }
+
+ udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf");
+ if (IS_ERR(udphy->vogrf)) {
+ if (PTR_ERR(udphy->vogrf) == -ENODEV) {
+ dev_warn(dev, "missing vo-grf dt node\n");
+ udphy->vogrf = NULL;
+ } else {
+ return PTR_ERR(udphy->vogrf);
+ }
+ }
+
+ ret = udphy_parse_lane_mux_data(udphy, np);
+ if (ret)
+ return ret;
+
+ if (dev_read_prop(dev, "maximum-speed", NULL)) {
+ maximum_speed = usb_get_maximum_speed(dev_ofnode(dev));
+ udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
+ }
+
+ ret = udphy_clk_init(udphy, dev);
+ if (ret)
+ return ret;
+
+ ret = udphy_reset_init(udphy, dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
+{
+ int ret;
+
+ if (!(udphy->mode & mode)) {
+ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
+ return 0;
+ }
+
+ if (udphy->status == UDPHY_MODE_NONE) {
+ udphy->mode_change = false;
+ ret = udphy_setup(udphy);
+ if (ret)
+ return ret;
+
+ if (udphy->mode & UDPHY_MODE_USB)
+ udphy_u3_port_disable(udphy, false);
+ } else if (udphy->mode_change) {
+ udphy->mode_change = false;
+ udphy->status = UDPHY_MODE_NONE;
+ if (udphy->mode == UDPHY_MODE_DP)
+ udphy_u3_port_disable(udphy, true);
+
+ ret = udphy_disable(udphy);
+ if (ret)
+ return ret;
+ ret = udphy_setup(udphy);
+ if (ret)
+ return ret;
+ }
+
+ udphy->status |= mode;
+
+ return 0;
+}
+
+static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
+{
+ int ret;
+
+ if (!(udphy->mode & mode)) {
+ dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
+ return 0;
+ }
+
+ if (!udphy->status)
+ return 0;
+
+ udphy->status &= ~mode;
+
+ if (udphy->status == UDPHY_MODE_NONE) {
+ ret = udphy_disable(udphy);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_u3phy_init(struct phy *phy)
+{
+ struct udevice *parent = phy->dev->parent;
+ struct rockchip_udphy *udphy = dev_get_priv(parent);
+
+ /* DP only or high-speed, disable U3 port */
+ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
+ udphy_u3_port_disable(udphy, true);
+ return 0;
+ }
+
+ return udphy_power_on(udphy, UDPHY_MODE_USB);
+}
+
+static int rockchip_u3phy_exit(struct phy *phy)
+{
+ struct udevice *parent = phy->dev->parent;
+ struct rockchip_udphy *udphy = dev_get_priv(parent);
+
+ /* DP only or high-speed */
+ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
+ return 0;
+
+ return udphy_power_off(udphy, UDPHY_MODE_USB);
+}
+
+static const struct phy_ops rockchip_u3phy_ops = {
+ .init = rockchip_u3phy_init,
+ .exit = rockchip_u3phy_exit,
+};
+
+int rockchip_u3phy_uboot_init(void)
+{
+ struct udevice *udev;
+ struct rockchip_udphy *udphy;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PHY,
+ DM_DRIVER_GET(rockchip_udphy_u3_port),
+ &udev);
+ if (ret) {
+ pr_err("%s: get u3-port failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* DP only or high-speed, disable U3 port */
+ udphy = dev_get_priv(udev->parent);
+ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
+ udphy_u3_port_disable(udphy, true);
+ return 0;
+ }
+
+ return udphy_power_on(udphy, UDPHY_MODE_USB);
+}
+
+static int rockchip_udphy_probe(struct udevice *dev)
+{
+ const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
+ struct rockchip_udphy *udphy = dev_get_priv(dev);
+ const struct rockchip_udphy_cfg *phy_cfgs;
+ int id, ret;
+
+ udphy->dev = dev;
+
+ id = of_alias_get_id(np, "usbdp");
+ if (id < 0)
+ id = 0;
+ udphy->id = id;
+
+ phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev);
+ if (!phy_cfgs) {
+ dev_err(dev, "unable to get phy_cfgs\n");
+ return -EINVAL;
+ }
+ udphy->cfgs = phy_cfgs;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap);
+ if (ret)
+ return ret;
+ udphy->pma_regmap->ranges[0].start += UDPHY_PMA;
+
+ ret = udphy_parse_dt(udphy, dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_udphy_bind(struct udevice *parent)
+{
+ struct udevice *child;
+ ofnode subnode;
+ const char *node_name;
+ int ret;
+
+ dev_for_each_subnode(subnode, parent) {
+ if (!ofnode_valid(subnode)) {
+ printf("%s: no subnode for %s", __func__, parent->name);
+ return -ENXIO;
+ }
+
+ node_name = ofnode_get_name(subnode);
+ debug("%s: subnode %s\n", __func__, node_name);
+
+ /* if there is no match, continue */
+ if (strcasecmp(node_name, "usb3-port"))
+ continue;
+
+ /* node name is usb3-port */
+ ret = device_bind_driver_to_node(parent,
+ "rockchip_udphy_u3_port",
+ node_name, subnode, &child);
+ if (ret) {
+ printf("%s: '%s' cannot bind its driver\n",
+ __func__, node_name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
+{
+ /* configure phy reference clock */
+ return __regmap_multi_reg_write(udphy->pma_regmap,
+ rk3588_udphy_24m_refclk_cfg,
+ ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
+}
+
+static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
+{
+ unsigned int val;
+ int ret;
+
+ if (!(udphy->mode & UDPHY_MODE_USB))
+ return 0;
+
+ /* LCPLL check */
+ ret = regmap_read_poll_timeout(udphy->pma_regmap,
+ CMN_ANA_LCPLL_DONE_OFFSET,
+ val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
+ (val & CMN_ANA_LCPLL_LOCK_DONE),
+ 200, 100);
+ if (ret) {
+ dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
+ return ret;
+ }
+
+ if (!udphy->flip) {
+ ret = regmap_read_poll_timeout(udphy->pma_regmap,
+ TRSV_LN0_MON_RX_CDR_DONE_OFFSET,
+ val,
+ val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
+ 200, 100);
+ if (ret)
+ dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
+ } else {
+ ret = regmap_read_poll_timeout(udphy->pma_regmap,
+ TRSV_LN2_MON_RX_CDR_DONE_OFFSET,
+ val,
+ val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
+ 200, 100);
+ if (ret)
+ dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
+ }
+
+ return 0;
+}
+
+static int rk3588_udphy_init(struct rockchip_udphy *udphy)
+{
+ const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
+ int ret;
+
+ /* enable rx lfps for usb */
+ if (udphy->mode & UDPHY_MODE_USB)
+ grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
+
+ /* Step 1: power on pma and deassert apb rstn */
+ grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
+
+ udphy_reset_deassert(udphy, "pma_apb");
+ udphy_reset_deassert(udphy, "pcs_apb");
+
+ /* Step 2: set init sequence and phy refclk */
+ ret = __regmap_multi_reg_write(udphy->pma_regmap,
+ rk3588_udphy_init_sequence,
+ ARRAY_SIZE(rk3588_udphy_init_sequence));
+ if (ret) {
+ dev_err(udphy->dev, "init sequence set error %d\n", ret);
+ goto assert_apb;
+ }
+
+ ret = rk3588_udphy_refclk_set(udphy);
+ if (ret) {
+ dev_err(udphy->dev, "refclk set error %d\n", ret);
+ goto assert_apb;
+ }
+
+ /* Step 3: configure lane mux */
+ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
+ CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
+ FIELD_PREP(CMN_DP_LANE_MUX_N(3),
+ udphy->lane_mux_sel[3]) |
+ FIELD_PREP(CMN_DP_LANE_MUX_N(2),
+ udphy->lane_mux_sel[2]) |
+ FIELD_PREP(CMN_DP_LANE_MUX_N(1),
+ udphy->lane_mux_sel[1]) |
+ FIELD_PREP(CMN_DP_LANE_MUX_N(0),
+ udphy->lane_mux_sel[0]) |
+ FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
+
+ /* Step 4: deassert init rstn and wait for 200ns from datasheet */
+ if (udphy->mode & UDPHY_MODE_USB)
+ udphy_reset_deassert(udphy, "init");
+
+ if (udphy->mode & UDPHY_MODE_DP) {
+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
+ CMN_DP_INIT_RSTN,
+ FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
+ }
+
+ udelay(1);
+
+ /* Step 5: deassert cmn/lane rstn */
+ if (udphy->mode & UDPHY_MODE_USB) {
+ udphy_reset_deassert(udphy, "cmn");
+ udphy_reset_deassert(udphy, "lane");
+ }
+
+ /* Step 6: wait for lock done of pll */
+ ret = rk3588_udphy_status_check(udphy);
+ if (ret)
+ goto assert_phy;
+
+ return 0;
+
+assert_phy:
+ udphy_reset_assert(udphy, "init");
+ udphy_reset_assert(udphy, "cmn");
+ udphy_reset_assert(udphy, "lane");
+
+assert_apb:
+ udphy_reset_assert(udphy, "pma_apb");
+ udphy_reset_assert(udphy, "pcs_apb");
+
+ return ret;
+}
+
+static const char * const rk3588_udphy_rst_l[] = {
+ "init", "cmn", "lane", "pcs_apb", "pma_apb"
+};
+
+static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
+ .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
+ .rst_list = rk3588_udphy_rst_l,
+ .grfcfg = {
+ /* u2phy-grf */
+ .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 },
+ .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 },
+
+ /* usb-grf */
+ .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 },
+ .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 },
+
+ /* usbdpphy-grf */
+ .low_pwrn = { 0x0004, 13, 13, 0, 1 },
+ .rx_lfps = { 0x0004, 14, 14, 0, 1 },
+ },
+ .combophy_init = rk3588_udphy_init,
+};
+
+static const struct udevice_id rockchip_udphy_dt_match[] = {
+ {
+ .compatible = "rockchip,rk3588-usbdp-phy",
+ .data = (ulong)&rk3588_udphy_cfgs
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rockchip_udphy_u3_port) = {
+ .name = "rockchip_udphy_u3_port",
+ .id = UCLASS_PHY,
+ .ops = &rockchip_u3phy_ops,
+};
+
+U_BOOT_DRIVER(rockchip_udphy) = {
+ .name = "rockchip_udphy",
+ .id = UCLASS_PHY,
+ .of_match = rockchip_udphy_dt_match,
+ .probe = rockchip_udphy_probe,
+ .bind = rockchip_udphy_bind,
+ .priv_auto = sizeof(struct rockchip_udphy),
+};
diff --git a/include/linux/usb/phy-rockchip-usbdp.h b/include/linux/usb/phy-rockchip-usbdp.h
new file mode 100644
index 000000000000..8acfa6ddf5a3
--- /dev/null
+++ b/include/linux/usb/phy-rockchip-usbdp.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Rockchip USBDP Combo PHY with Samsung IP block driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __PHY_ROCKCHIP_USBDP_H_
+#define __PHY_ROCKCHIP_USBDP_H_
+
+#include <linux/bitops.h>
+
+/* RK3588 USBDP PHY Register Definitions */
+
+#define UDPHY_PCS 0x4000
+#define UDPHY_PMA 0x8000
+
+/* VO0 GRF Registers */
+#define RK3588_GRF_VO0_CON0 0x0000
+#define RK3588_GRF_VO0_CON2 0x0008
+#define DP_SINK_HPD_CFG BIT(11)
+#define DP_SINK_HPD_SEL BIT(10)
+#define DP_AUX_DIN_SEL BIT(9)
+#define DP_AUX_DOUT_SEL BIT(8)
+#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))
+#define DP_LANE_SEL_ALL GENMASK(7, 0)
+#define PHY_AUX_DP_DATA_POL_NORMAL 0
+#define PHY_AUX_DP_DATA_POL_INVERT 1
+
+/* PMA CMN Registers */
+#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
+#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4)
+#define CMN_DP_LANE_EN_N(n) BIT(n)
+#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)
+#define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
+#define PHY_LANE_MUX_USB 0
+#define PHY_LANE_MUX_DP 1
+
+#define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */
+#define CMN_DP_TX_LINK_BW GENMASK(6, 5)
+#define CMN_DP_TX_LANE_SWAP_EN BIT(2)
+
+#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
+#define CMN_ROPLL_SSC_EN BIT(1)
+#define CMN_LCPLL_SSC_EN BIT(0)
+
+#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
+#define CMN_ANA_LCPLL_LOCK_DONE BIT(7)
+#define CMN_ANA_LCPLL_AFC_DONE BIT(6)
+
+#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
+#define CMN_ANA_ROPLL_LOCK_DONE BIT(1)
+#define CMN_ANA_ROPLL_AFC_DONE BIT(0)
+
+#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */
+#define CMN_DP_INIT_RSTN BIT(3)
+#define CMN_DP_CMN_RSTN BIT(2)
+#define CMN_CDR_WTCHDG_EN BIT(1)
+#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0)
+
+#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */
+#define LN_ANA_TX_SER_TXCLK_INV BIT(1)
+
+#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */
+#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
+
+#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */
+#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0)
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] ARM: dts: rockchip: rk3588: add support for USB 3.0 devices
2023-05-29 10:01 [PATCH 0/4] rockchip: rk3588: add USB 3.0 support Eugen Hristev
2023-05-29 10:01 ` [PATCH 1/4] phy: rockchip: add usbdp combo phy driver Eugen Hristev
@ 2023-05-29 10:01 ` Eugen Hristev
2023-07-26 7:35 ` Kever Yang
2023-05-29 10:01 ` [PATCH 3/4] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support Eugen Hristev
2023-05-29 10:01 ` [PATCH 4/4] configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget Eugen Hristev
3 siblings, 1 reply; 9+ messages in thread
From: Eugen Hristev @ 2023-05-29 10:01 UTC (permalink / raw)
To: u-boot, kever.yang, jonas, jagan; +Cc: eugen.hristev, Joseph Chen
From: Joseph Chen <chenjh@rock-chips.com>
Add support for the USB 3.0 devices in rk3588:
- USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in
rk3588s
- USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in
rk3588 only
- USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface
as usbdp_phy0
- USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface
as usbdp_phy1
- USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0
mode
- associated GRFs (general register files) for the devices.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
[eugen.hristev@collabora.com: move nodes to right place, adapt from latest
linux kernel]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
---
arch/arm/dts/rk3588-u-boot.dtsi | 93 +++++++++++++++++++++++++++
arch/arm/dts/rk3588s-u-boot.dtsi | 105 +++++++++++++++++++++++++++++++
2 files changed, 198 insertions(+)
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
index 4c8ac804d615..68b419f3abd5 100644
--- a/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -5,3 +5,96 @@
#include "rockchip-u-boot.dtsi"
#include "rk3588s-u-boot.dtsi"
+
+/ {
+ usbdrd3_1: usbdrd3_1 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref", "suspend", "bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3_1: usb@fc400000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfc400000 0x0 0x400000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ reset-names = "usb3-otg";
+ dr_mode = "host";
+ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ };
+ };
+
+ usbdpphy1_grf: syscon@fd5cc000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
+ };
+
+ usb2phy1_grf: syscon@fd5d4000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy1: usb2-phy@4000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x4000 0x10>;
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ #clock-cells = <0>;
+ rockchip,usbctrl-grf = <&usb_grf>;
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ usbdp_phy1: phy@fed90000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed90000 0x0 0x10000>;
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
+ <&cru PCLK_USBDPPHY1>,
+ <&u2phy1>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
+ <&cru SRST_P_USBDPPHY1>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ status = "disabled";
+
+ usbdp_phy1_dp: dp-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbdp_phy1_u3: usb3-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 1bb3c6a9d958..acb1cfe20063 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -13,6 +13,37 @@
status = "okay";
};
+ usbdrd3_0: usbdrd3_0 {
+ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref", "suspend", "bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3_0: usb@fc000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfc000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG0>;
+ reset-names = "usb3-otg";
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ quirk-skip-phy-init;
+ };
+ };
+
usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";
reg = <0x0 0xfc800000 0x0 0x40000>;
@@ -64,6 +95,33 @@
reg = <0x0 0xfd5bc000 0x0 0x100>;
};
+ usb2phy0_grf: syscon@fd5d0000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy0: usb2-phy@0 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x0 0x10>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy0";
+ #clock-cells = <0>;
+ rockchip,usbctrl-grf = <&usb_grf>;
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
@@ -87,6 +145,17 @@
};
};
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = <&cru PCLK_VO0GRF>;
+ };
+
+ usb_grf: syscon@fd5ac000 {
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
+ };
+
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
@@ -110,6 +179,11 @@
};
};
+ usbdpphy0_grf: syscon@fd5c8000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
+ };
+
pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
#address-cells = <3>;
@@ -180,6 +254,37 @@
status = "disabled";
};
+ usbdp_phy0: phy@fed80000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed80000 0x0 0x10000>;
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
+ <&cru PCLK_USBDPPHY0>,
+ <&u2phy0>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
+ <&cru SRST_P_USBDPPHY0>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ status = "disabled";
+
+ usbdp_phy0_dp: dp-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbdp_phy0_u3: usb3-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support
2023-05-29 10:01 [PATCH 0/4] rockchip: rk3588: add USB 3.0 support Eugen Hristev
2023-05-29 10:01 ` [PATCH 1/4] phy: rockchip: add usbdp combo phy driver Eugen Hristev
2023-05-29 10:01 ` [PATCH 2/4] ARM: dts: rockchip: rk3588: add support for USB 3.0 devices Eugen Hristev
@ 2023-05-29 10:01 ` Eugen Hristev
2023-07-26 7:36 ` Kever Yang
2023-05-29 10:01 ` [PATCH 4/4] configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget Eugen Hristev
3 siblings, 1 reply; 9+ messages in thread
From: Eugen Hristev @ 2023-05-29 10:01 UTC (permalink / raw)
To: u-boot, kever.yang, jonas, jagan; +Cc: eugen.hristev
Enable the USB3.0 host node, and gadget node.
The gadget is available through the USB type C connector on the board.
The connector is tied to a Fairchild fusb302b device, which currently
does not have a driver in U-boot, but the node is here for correct
description of the board + Linux future compatibility.
It will be easier to move the node as-is when it will be available
in the DT from Linux
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
---
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 197 ++++++++++++++++++++++++
1 file changed, 197 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 1cd8a57a6fa6..5a3292699640 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/usb/pd.h>
/ {
aliases {
@@ -18,6 +19,25 @@
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
@@ -29,6 +49,28 @@
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_sys>;
};
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+
+ vbus5v0_typec: vbus5v0-typec {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_usb>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ };
};
&combphy0_ps {
@@ -85,6 +127,16 @@
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pcfg_pull_none {
@@ -168,6 +220,15 @@
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ rockchip,typec-vbus-det;
+ status = "okay";
+};
+
&u2phy2 {
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
reset-names = "phy", "apb";
@@ -209,3 +270,139 @@
status = "okay";
};
+&usbdp_phy0 {
+ orientation-switch;
+ svid = <0xff01>;
+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usbdp_phy0_orientation_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_orien_sw>;
+ };
+
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dp_altmode_mux>;
+ };
+ };
+};
+
+&usbdp_phy0_u3 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+ usb-role-switch;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dwc3_0_role_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_role_sw>;
+ };
+ };
+};
+
+&usbdp_phy1 {
+ rockchip,dp-lane-mux = <2 3>;
+ status = "okay";
+};
+
+&usbdp_phy1_u3 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-0 = <&i2c4m1_xfer>;
+ status = "okay";
+
+ usbc0: fusb302@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus5v0_typec>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_role_sw: endpoint@0 {
+ remote-endpoint = <&dwc3_0_role_switch>;
+ };
+ };
+ };
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ op-sink-microwatt = <1000000>;
+ sink-pdos =
+ <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ altmodes {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ altmode@0 {
+ reg = <0>;
+ svid = <0xff01>;
+ vdo = <0xffffffff>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_orien_sw: endpoint {
+ remote-endpoint = <&usbdp_phy0_orientation_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_altmode_mux: endpoint {
+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+ };
+ };
+ };
+ };
+ };
+};
+
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget
2023-05-29 10:01 [PATCH 0/4] rockchip: rk3588: add USB 3.0 support Eugen Hristev
` (2 preceding siblings ...)
2023-05-29 10:01 ` [PATCH 3/4] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support Eugen Hristev
@ 2023-05-29 10:01 ` Eugen Hristev
2023-07-26 7:36 ` Kever Yang
3 siblings, 1 reply; 9+ messages in thread
From: Eugen Hristev @ 2023-05-29 10:01 UTC (permalink / raw)
To: u-boot, kever.yang, jonas, jagan; +Cc: eugen.hristev
Enable configuration for USB 3.0 controller, the commands required,
and the gadget drivers.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
---
configs/rock5b-rk3588_defconfig | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index a4a3c0afd178..3f28a68f0c94 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -47,9 +47,11 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
@@ -59,6 +61,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@@ -76,6 +79,7 @@ CONFIG_GMAC_ROCKCHIP=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
@@ -86,10 +90,16 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
@@ -98,4 +108,8 @@ CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350b
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] phy: rockchip: add usbdp combo phy driver
2023-05-29 10:01 ` [PATCH 1/4] phy: rockchip: add usbdp combo phy driver Eugen Hristev
@ 2023-07-26 7:29 ` Kever Yang
0 siblings, 0 replies; 9+ messages in thread
From: Kever Yang @ 2023-07-26 7:29 UTC (permalink / raw)
To: Eugen Hristev, u-boot, jonas, jagan; +Cc: Frank Wang
On 2023/5/29 18:01, Eugen Hristev wrote:
> From: Frank Wang <frank.wang@rock-chips.com>
>
> This adds a new USBDP combo PHY with Samsung IP block driver.
> The PHY is a combo between USB 3.0 and DisplayPort alt mode.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> [eugen.hristev@collabora.com: ported to 2023.07, clean-up]
> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> drivers/phy/rockchip/Kconfig | 7 +
> drivers/phy/rockchip/Makefile | 1 +
> drivers/phy/rockchip/phy-rockchip-usbdp.c | 880 ++++++++++++++++++++++
> include/linux/usb/phy-rockchip-usbdp.h | 70 ++
> 4 files changed, 958 insertions(+)
> create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
> create mode 100644 include/linux/usb/phy-rockchip-usbdp.h
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index f87ca8c31060..0247d93ab401 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -41,6 +41,13 @@ config PHY_ROCKCHIP_SNPS_PCIE3
> It could support PCIe Gen3 single root complex, and could
> also be able splited into multiple combinations of lanes.
>
> +config PHY_ROCKCHIP_USBDP
> + tristate "Rockchip USBDP COMBO PHY Driver"
> + depends on ARCH_ROCKCHIP
> + select PHY
> + help
> + Enable this to support the Rockchip USB3.0/DP
> + combo PHY with Samsung IP block.
>
> config PHY_ROCKCHIP_TYPEC
> bool "Rockchip TYPEC PHY Driver"
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index 25a803a8a86f..7fdbd107976d 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
> obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
> obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
> obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
> +obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
> new file mode 100644
> index 000000000000..baf92529348c
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
> @@ -0,0 +1,880 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Rockchip USBDP Combo PHY with Samsung IP block driver
> + *
> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dm/device_compat.h>
> +#include <dm/devres.h>
> +#include <dm/lists.h>
> +#include <dm/of.h>
> +#include <dm/of_access.h>
> +#include <generic-phy.h>
> +#include <linux/bitfield.h>
> +#include <linux/usb/ch9.h>
> +#include <linux/usb/otg.h>
> +#include <regmap.h>
> +#include <reset.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +#include <linux/usb/phy-rockchip-usbdp.h>
> +
> +#define BIT_WRITEABLE_SHIFT 16
> +
> +enum {
> + UDPHY_MODE_NONE = 0,
> + UDPHY_MODE_USB = BIT(0),
> + UDPHY_MODE_DP = BIT(1),
> + UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
> +};
> +
> +struct udphy_grf_reg {
> + unsigned int offset;
> + unsigned int bitend;
> + unsigned int bitstart;
> + unsigned int disable;
> + unsigned int enable;
> +};
> +
> +/**
> + * struct reg_sequence - An individual write from a sequence of writes.
> + *
> + * @reg: Register address.
> + * @def: Register value.
> + * @delay_us: Delay to be applied after the register write in microseconds
> + *
> + * Register/value pairs for sequences of writes with an optional delay in
> + * microseconds to be applied after each write.
> + */
> +struct reg_sequence {
> + unsigned int reg;
> + unsigned int def;
> + unsigned int delay_us;
> +};
> +
> +struct udphy_grf_cfg {
> + /* u2phy-grf */
> + struct udphy_grf_reg bvalid_phy_con;
> + struct udphy_grf_reg bvalid_grf_con;
> +
> + /* usb-grf */
> + struct udphy_grf_reg usb3otg0_cfg;
> + struct udphy_grf_reg usb3otg1_cfg;
> +
> + /* usbdpphy-grf */
> + struct udphy_grf_reg low_pwrn;
> + struct udphy_grf_reg rx_lfps;
> +};
> +
> +struct rockchip_udphy;
> +
> +struct rockchip_udphy_cfg {
> + /* resets to be requested */
> + const char * const *rst_list;
> + int num_rsts;
> +
> + struct udphy_grf_cfg grfcfg;
> + int (*combophy_init)(struct rockchip_udphy *udphy);
> +};
> +
> +struct rockchip_udphy {
> + struct udevice *dev;
> + struct regmap *pma_regmap;
> + struct regmap *u2phygrf;
> + struct regmap *udphygrf;
> + struct regmap *usbgrf;
> + struct regmap *vogrf;
> +
> + /* clocks and rests */
> + struct reset_ctl *rsts;
> +
> + /* PHY status management */
> + bool flip;
> + bool mode_change;
> + u8 mode;
> + u8 status;
> +
> + /* utilized for USB */
> + bool hs; /* flag for high-speed */
> +
> + /* utilized for DP */
> + struct gpio_desc *sbu1_dc_gpio;
> + struct gpio_desc *sbu2_dc_gpio;
> + u32 lane_mux_sel[4];
> + u32 dp_lane_sel[4];
> + u32 dp_aux_dout_sel;
> + u32 dp_aux_din_sel;
> + int id;
> +
> + /* PHY const config */
> + const struct rockchip_udphy_cfg *cfgs;
> +};
> +
> +static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
> + {0x0090, 0x68}, {0x0094, 0x68},
> + {0x0128, 0x24}, {0x012c, 0x44},
> + {0x0130, 0x3f}, {0x0134, 0x44},
> + {0x015c, 0xa9}, {0x0160, 0x71},
> + {0x0164, 0x71}, {0x0168, 0xa9},
> + {0x0174, 0xa9}, {0x0178, 0x71},
> + {0x017c, 0x71}, {0x0180, 0xa9},
> + {0x018c, 0x41}, {0x0190, 0x00},
> + {0x0194, 0x05}, {0x01ac, 0x2a},
> + {0x01b0, 0x17}, {0x01b4, 0x17},
> + {0x01b8, 0x2a}, {0x01c8, 0x04},
> + {0x01cc, 0x08}, {0x01d0, 0x08},
> + {0x01d4, 0x04}, {0x01d8, 0x20},
> + {0x01dc, 0x01}, {0x01e0, 0x09},
> + {0x01e4, 0x03}, {0x01f0, 0x29},
> + {0x01f4, 0x02}, {0x01f8, 0x02},
> + {0x01fc, 0x29}, {0x0208, 0x2a},
> + {0x020c, 0x17}, {0x0210, 0x17},
> + {0x0214, 0x2a}, {0x0224, 0x20},
> + {0x03f0, 0x0d}, {0x03f4, 0x09},
> + {0x03f8, 0x09}, {0x03fc, 0x0d},
> + {0x0404, 0x0e}, {0x0408, 0x14},
> + {0x040c, 0x14}, {0x0410, 0x3b},
> + {0x0ce0, 0x68}, {0x0ce8, 0xd0},
> + {0x0cf0, 0x87}, {0x0cf8, 0x70},
> + {0x0d00, 0x70}, {0x0d08, 0xa9},
> + {0x1ce0, 0x68}, {0x1ce8, 0xd0},
> + {0x1cf0, 0x87}, {0x1cf8, 0x70},
> + {0x1d00, 0x70}, {0x1d08, 0xa9},
> + {0x0a3c, 0xd0}, {0x0a44, 0xd0},
> + {0x0a48, 0x01}, {0x0a4c, 0x0d},
> + {0x0a54, 0xe0}, {0x0a5c, 0xe0},
> + {0x0a64, 0xa8}, {0x1a3c, 0xd0},
> + {0x1a44, 0xd0}, {0x1a48, 0x01},
> + {0x1a4c, 0x0d}, {0x1a54, 0xe0},
> + {0x1a5c, 0xe0}, {0x1a64, 0xa8}
> +};
> +
> +static const struct reg_sequence rk3588_udphy_init_sequence[] = {
> + {0x0104, 0x44}, {0x0234, 0xE8},
> + {0x0248, 0x44}, {0x028C, 0x18},
> + {0x081C, 0xE5}, {0x0878, 0x00},
> + {0x0994, 0x1C}, {0x0AF0, 0x00},
> + {0x181C, 0xE5}, {0x1878, 0x00},
> + {0x1994, 0x1C}, {0x1AF0, 0x00},
> + {0x0428, 0x60}, {0x0D58, 0x33},
> + {0x1D58, 0x33}, {0x0990, 0x74},
> + {0x0D64, 0x17}, {0x08C8, 0x13},
> + {0x1990, 0x74}, {0x1D64, 0x17},
> + {0x18C8, 0x13}, {0x0D90, 0x40},
> + {0x0DA8, 0x40}, {0x0DC0, 0x40},
> + {0x0DD8, 0x40}, {0x1D90, 0x40},
> + {0x1DA8, 0x40}, {0x1DC0, 0x40},
> + {0x1DD8, 0x40}, {0x03C0, 0x30},
> + {0x03C4, 0x06}, {0x0E10, 0x00},
> + {0x1E10, 0x00}, {0x043C, 0x0F},
> + {0x0D2C, 0xFF}, {0x1D2C, 0xFF},
> + {0x0D34, 0x0F}, {0x1D34, 0x0F},
> + {0x08FC, 0x2A}, {0x0914, 0x28},
> + {0x0A30, 0x03}, {0x0E38, 0x05},
> + {0x0ECC, 0x27}, {0x0ED0, 0x22},
> + {0x0ED4, 0x26}, {0x18FC, 0x2A},
> + {0x1914, 0x28}, {0x1A30, 0x03},
> + {0x1E38, 0x05}, {0x1ECC, 0x27},
> + {0x1ED0, 0x22}, {0x1ED4, 0x26},
> + {0x0048, 0x0F}, {0x0060, 0x3C},
> + {0x0064, 0xF7}, {0x006C, 0x20},
> + {0x0070, 0x7D}, {0x0074, 0x68},
> + {0x0AF4, 0x1A}, {0x1AF4, 0x1A},
> + {0x0440, 0x3F}, {0x10D4, 0x08},
> + {0x20D4, 0x08}, {0x00D4, 0x30},
> + {0x0024, 0x6e},
> +};
> +
> +static inline int grfreg_write(struct regmap *base,
> + const struct udphy_grf_reg *reg, bool en)
> +{
> + u32 val, mask, tmp;
> +
> + tmp = en ? reg->enable : reg->disable;
> + mask = GENMASK(reg->bitend, reg->bitstart);
> + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
> +
> + return regmap_write(base, reg->offset, val);
> +}
> +
> +static int __regmap_multi_reg_write(struct regmap *map,
> + const struct reg_sequence *regs,
> + int num_regs)
> +{
> + int i, ret = 0;
> +
> + for (i = 0; i < num_regs; i++) {
> + ret = regmap_write(map, regs[i].reg, regs[i].def);
> +
> + if (regs[i].delay_us)
> + udelay(regs[i].delay_us);
> + }
> +
> + return ret;
> +}
> +
> +static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev)
> +{
> + return 0;
> +}
> +
> +static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev)
> +{
> + const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
> + int idx;
> + int ret;
> +
> + udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
> + sizeof(*udphy->rsts), GFP_KERNEL);
> + if (!udphy->rsts)
> + return -ENOMEM;
> +
> + for (idx = 0; idx < cfg->num_rsts; idx++) {
> + const char *name = cfg->rst_list[idx];
> +
> + ret = reset_get_by_name(dev, name, &udphy->rsts[idx]);
> + if (ret) {
> + dev_err(dev, "failed to get %s reset\n", name);
> + goto err;
> + }
> +
> + reset_assert(&udphy->rsts[idx]);
> + }
> +
> + return 0;
> +
> +err:
> + devm_kfree(dev, udphy->rsts);
> + return ret;
> +}
> +
> +static int udphy_get_rst_idx(const char * const *list, int num, char *name)
> +{
> + int idx;
> +
> + for (idx = 0; idx < num; idx++) {
> + if (!strcmp(list[idx], name))
> + return idx;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
> +{
> + const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
> + int idx;
> +
> + idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
> + if (idx < 0)
> + return idx;
> +
> + return reset_assert(&udphy->rsts[idx]);
> +}
> +
> +static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
> +{
> + const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
> + int idx;
> +
> + idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
> + if (idx < 0)
> + return idx;
> +
> + return reset_deassert(&udphy->rsts[idx]);
> +}
> +
> +static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
> +{
> + const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
> + const struct udphy_grf_reg *preg;
> +
> + preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
> + grfreg_write(udphy->usbgrf, preg, disable);
> +}
> +
> +__maybe_unused
> +static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
> +{
> + const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
> +
> + grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
> + grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
> +}
> +
> +/*
> + * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
> + *
> + * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
> + * ---------------------------------------------------------------------------
> + * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
> + * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
> + * C/E(Normal) dpln3 dpln2 dpln0 dpln1
> + * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
> + * D/F(Normal) usbrx usbtx dpln0 dpln1
> + * D/F(Flip ) dpln0 dpln1 usbrx usbtx
> + * A(Normal ) dpln3 dpln1 dpln2 dpln0
> + * A(Flip ) dpln2 dpln0 dpln3 dpln1
> + * B(Normal ) usbrx usbtx dpln1 dpln0
> + * B(Flip ) dpln1 dpln0 usbrx usbtx
> + * ---------------------------------------------------------------------------
> + *
> + * 2 Mapping the lanes in dtsi
> + * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
> + * sample as follow:
> + * ---------------------------------------------------------------------------
> + * B11-B10 A2-A3 A11-A10 B2-B3
> + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
> + * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
> + * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
> + * ---------------------------------------------------------------------------
> + * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
> + * sample as follow:
> + * ---------------------------------------------------------------------------
> + * B11-B10 A2-A3 A11-A10 B2-B3
> + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
> + * <0 1> dpln0 dpln1 usbrx usbtx
> + * <2 3> usbrx usbtx dpln0 dpln1
> + * ---------------------------------------------------------------------------
> + */
> +
> +__maybe_unused
> +static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
> +{
> + if (udphy->flip) {
> + udphy->dp_lane_sel[0] = 0;
> + udphy->dp_lane_sel[1] = 1;
> + udphy->dp_lane_sel[2] = 3;
> + udphy->dp_lane_sel[3] = 2;
> + udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
> + udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
> + udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
> + udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
> + udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
> + udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
> + } else {
> + udphy->dp_lane_sel[0] = 2;
> + udphy->dp_lane_sel[1] = 3;
> + udphy->dp_lane_sel[2] = 1;
> + udphy->dp_lane_sel[3] = 0;
> + udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
> + udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
> + udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
> + udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
> + udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
> + udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
> + }
> +
> + udphy->mode = UDPHY_MODE_DP_USB;
> +
> + return 0;
> +}
> +
> +static int udphy_setup(struct rockchip_udphy *udphy)
> +{
> + const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
> + int ret = 0;
> +
> + if (cfg->combophy_init) {
> + ret = cfg->combophy_init(udphy);
> + if (ret)
> + dev_err(udphy->dev, "failed to init usbdp combophy\n");
> + }
> +
> + return ret;
> +}
> +
> +static int udphy_disable(struct rockchip_udphy *udphy)
> +{
> + const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
> + int i;
> +
> + for (i = 0; i < cfg->num_rsts; i++)
> + reset_assert(&udphy->rsts[i]);
> +
> + return 0;
> +}
> +
> +static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy,
> + const struct device_node *np)
> +{
> + struct property *prop;
> + int ret, i, len, num_lanes;
> +
> + prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
> + if (!prop) {
> + dev_dbg(udphy->dev,
> + "failed to find dp lane mux, following dp alt mode\n");
> + udphy->mode = UDPHY_MODE_USB;
> + return 0;
> + }
> +
> + num_lanes = len / sizeof(u32);
> +
> + if (num_lanes != 2 && num_lanes != 4) {
> + dev_err(udphy->dev, "invalid number of lane mux\n");
> + return -EINVAL;
> + }
> +
> + ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel,
> + num_lanes);
> + if (ret) {
> + dev_err(udphy->dev, "get dp lane mux failed\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < num_lanes; i++) {
> + int j;
> +
> + if (udphy->dp_lane_sel[i] > 3) {
> + dev_err(udphy->dev,
> + "lane mux between 0 and 3, exceeding the range\n");
> + return -EINVAL;
> + }
> +
> + udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
> +
> + for (j = i + 1; j < num_lanes; j++) {
> + if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
> + dev_err(udphy->dev,
> + "set repeat lane mux value\n");
> + return -EINVAL;
> + }
> + }
> + }
> +
> + udphy->mode = UDPHY_MODE_DP;
> + if (num_lanes == 2)
> + udphy->mode |= UDPHY_MODE_USB;
> +
> + return 0;
> +}
> +
> +static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
> +{
> + const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
> + enum usb_device_speed maximum_speed;
> + int ret;
> +
> + udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev,
> + "rockchip,u2phy-grf");
> + if (IS_ERR(udphy->u2phygrf)) {
> + if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
> + dev_warn(dev, "missing u2phy-grf dt node\n");
> + udphy->u2phygrf = NULL;
> + } else {
> + return PTR_ERR(udphy->u2phygrf);
> + }
> + }
> +
> + udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev,
> + "rockchip,usbdpphy-grf");
> + if (IS_ERR(udphy->udphygrf)) {
> + if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
> + dev_warn(dev, "missing usbdpphy-grf dt node\n");
> + udphy->udphygrf = NULL;
> + } else {
> + return PTR_ERR(udphy->udphygrf);
> + }
> + }
> +
> + udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev,
> + "rockchip,usb-grf");
> + if (IS_ERR(udphy->usbgrf)) {
> + if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
> + dev_warn(dev, "missing usb-grf dt node\n");
> + udphy->usbgrf = NULL;
> + } else {
> + return PTR_ERR(udphy->usbgrf);
> + }
> + }
> +
> + udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf");
> + if (IS_ERR(udphy->vogrf)) {
> + if (PTR_ERR(udphy->vogrf) == -ENODEV) {
> + dev_warn(dev, "missing vo-grf dt node\n");
> + udphy->vogrf = NULL;
> + } else {
> + return PTR_ERR(udphy->vogrf);
> + }
> + }
> +
> + ret = udphy_parse_lane_mux_data(udphy, np);
> + if (ret)
> + return ret;
> +
> + if (dev_read_prop(dev, "maximum-speed", NULL)) {
> + maximum_speed = usb_get_maximum_speed(dev_ofnode(dev));
> + udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
> + }
> +
> + ret = udphy_clk_init(udphy, dev);
> + if (ret)
> + return ret;
> +
> + ret = udphy_reset_init(udphy, dev);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
> +{
> + int ret;
> +
> + if (!(udphy->mode & mode)) {
> + dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
> + return 0;
> + }
> +
> + if (udphy->status == UDPHY_MODE_NONE) {
> + udphy->mode_change = false;
> + ret = udphy_setup(udphy);
> + if (ret)
> + return ret;
> +
> + if (udphy->mode & UDPHY_MODE_USB)
> + udphy_u3_port_disable(udphy, false);
> + } else if (udphy->mode_change) {
> + udphy->mode_change = false;
> + udphy->status = UDPHY_MODE_NONE;
> + if (udphy->mode == UDPHY_MODE_DP)
> + udphy_u3_port_disable(udphy, true);
> +
> + ret = udphy_disable(udphy);
> + if (ret)
> + return ret;
> + ret = udphy_setup(udphy);
> + if (ret)
> + return ret;
> + }
> +
> + udphy->status |= mode;
> +
> + return 0;
> +}
> +
> +static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
> +{
> + int ret;
> +
> + if (!(udphy->mode & mode)) {
> + dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
> + return 0;
> + }
> +
> + if (!udphy->status)
> + return 0;
> +
> + udphy->status &= ~mode;
> +
> + if (udphy->status == UDPHY_MODE_NONE) {
> + ret = udphy_disable(udphy);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_u3phy_init(struct phy *phy)
> +{
> + struct udevice *parent = phy->dev->parent;
> + struct rockchip_udphy *udphy = dev_get_priv(parent);
> +
> + /* DP only or high-speed, disable U3 port */
> + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
> + udphy_u3_port_disable(udphy, true);
> + return 0;
> + }
> +
> + return udphy_power_on(udphy, UDPHY_MODE_USB);
> +}
> +
> +static int rockchip_u3phy_exit(struct phy *phy)
> +{
> + struct udevice *parent = phy->dev->parent;
> + struct rockchip_udphy *udphy = dev_get_priv(parent);
> +
> + /* DP only or high-speed */
> + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
> + return 0;
> +
> + return udphy_power_off(udphy, UDPHY_MODE_USB);
> +}
> +
> +static const struct phy_ops rockchip_u3phy_ops = {
> + .init = rockchip_u3phy_init,
> + .exit = rockchip_u3phy_exit,
> +};
> +
> +int rockchip_u3phy_uboot_init(void)
> +{
> + struct udevice *udev;
> + struct rockchip_udphy *udphy;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(UCLASS_PHY,
> + DM_DRIVER_GET(rockchip_udphy_u3_port),
> + &udev);
> + if (ret) {
> + pr_err("%s: get u3-port failed: %d\n", __func__, ret);
> + return ret;
> + }
> +
> + /* DP only or high-speed, disable U3 port */
> + udphy = dev_get_priv(udev->parent);
> + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
> + udphy_u3_port_disable(udphy, true);
> + return 0;
> + }
> +
> + return udphy_power_on(udphy, UDPHY_MODE_USB);
> +}
> +
> +static int rockchip_udphy_probe(struct udevice *dev)
> +{
> + const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
> + struct rockchip_udphy *udphy = dev_get_priv(dev);
> + const struct rockchip_udphy_cfg *phy_cfgs;
> + int id, ret;
> +
> + udphy->dev = dev;
> +
> + id = of_alias_get_id(np, "usbdp");
> + if (id < 0)
> + id = 0;
> + udphy->id = id;
> +
> + phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev);
> + if (!phy_cfgs) {
> + dev_err(dev, "unable to get phy_cfgs\n");
> + return -EINVAL;
> + }
> + udphy->cfgs = phy_cfgs;
> +
> + ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap);
> + if (ret)
> + return ret;
> + udphy->pma_regmap->ranges[0].start += UDPHY_PMA;
> +
> + ret = udphy_parse_dt(udphy, dev);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int rockchip_udphy_bind(struct udevice *parent)
> +{
> + struct udevice *child;
> + ofnode subnode;
> + const char *node_name;
> + int ret;
> +
> + dev_for_each_subnode(subnode, parent) {
> + if (!ofnode_valid(subnode)) {
> + printf("%s: no subnode for %s", __func__, parent->name);
> + return -ENXIO;
> + }
> +
> + node_name = ofnode_get_name(subnode);
> + debug("%s: subnode %s\n", __func__, node_name);
> +
> + /* if there is no match, continue */
> + if (strcasecmp(node_name, "usb3-port"))
> + continue;
> +
> + /* node name is usb3-port */
> + ret = device_bind_driver_to_node(parent,
> + "rockchip_udphy_u3_port",
> + node_name, subnode, &child);
> + if (ret) {
> + printf("%s: '%s' cannot bind its driver\n",
> + __func__, node_name);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
> +{
> + /* configure phy reference clock */
> + return __regmap_multi_reg_write(udphy->pma_regmap,
> + rk3588_udphy_24m_refclk_cfg,
> + ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
> +}
> +
> +static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
> +{
> + unsigned int val;
> + int ret;
> +
> + if (!(udphy->mode & UDPHY_MODE_USB))
> + return 0;
> +
> + /* LCPLL check */
> + ret = regmap_read_poll_timeout(udphy->pma_regmap,
> + CMN_ANA_LCPLL_DONE_OFFSET,
> + val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
> + (val & CMN_ANA_LCPLL_LOCK_DONE),
> + 200, 100);
> + if (ret) {
> + dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
> + return ret;
> + }
> +
> + if (!udphy->flip) {
> + ret = regmap_read_poll_timeout(udphy->pma_regmap,
> + TRSV_LN0_MON_RX_CDR_DONE_OFFSET,
> + val,
> + val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
> + 200, 100);
> + if (ret)
> + dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
> + } else {
> + ret = regmap_read_poll_timeout(udphy->pma_regmap,
> + TRSV_LN2_MON_RX_CDR_DONE_OFFSET,
> + val,
> + val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
> + 200, 100);
> + if (ret)
> + dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
> + }
> +
> + return 0;
> +}
> +
> +static int rk3588_udphy_init(struct rockchip_udphy *udphy)
> +{
> + const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
> + int ret;
> +
> + /* enable rx lfps for usb */
> + if (udphy->mode & UDPHY_MODE_USB)
> + grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
> +
> + /* Step 1: power on pma and deassert apb rstn */
> + grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
> +
> + udphy_reset_deassert(udphy, "pma_apb");
> + udphy_reset_deassert(udphy, "pcs_apb");
> +
> + /* Step 2: set init sequence and phy refclk */
> + ret = __regmap_multi_reg_write(udphy->pma_regmap,
> + rk3588_udphy_init_sequence,
> + ARRAY_SIZE(rk3588_udphy_init_sequence));
> + if (ret) {
> + dev_err(udphy->dev, "init sequence set error %d\n", ret);
> + goto assert_apb;
> + }
> +
> + ret = rk3588_udphy_refclk_set(udphy);
> + if (ret) {
> + dev_err(udphy->dev, "refclk set error %d\n", ret);
> + goto assert_apb;
> + }
> +
> + /* Step 3: configure lane mux */
> + regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
> + CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
> + FIELD_PREP(CMN_DP_LANE_MUX_N(3),
> + udphy->lane_mux_sel[3]) |
> + FIELD_PREP(CMN_DP_LANE_MUX_N(2),
> + udphy->lane_mux_sel[2]) |
> + FIELD_PREP(CMN_DP_LANE_MUX_N(1),
> + udphy->lane_mux_sel[1]) |
> + FIELD_PREP(CMN_DP_LANE_MUX_N(0),
> + udphy->lane_mux_sel[0]) |
> + FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
> +
> + /* Step 4: deassert init rstn and wait for 200ns from datasheet */
> + if (udphy->mode & UDPHY_MODE_USB)
> + udphy_reset_deassert(udphy, "init");
> +
> + if (udphy->mode & UDPHY_MODE_DP) {
> + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
> + CMN_DP_INIT_RSTN,
> + FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
> + }
> +
> + udelay(1);
> +
> + /* Step 5: deassert cmn/lane rstn */
> + if (udphy->mode & UDPHY_MODE_USB) {
> + udphy_reset_deassert(udphy, "cmn");
> + udphy_reset_deassert(udphy, "lane");
> + }
> +
> + /* Step 6: wait for lock done of pll */
> + ret = rk3588_udphy_status_check(udphy);
> + if (ret)
> + goto assert_phy;
> +
> + return 0;
> +
> +assert_phy:
> + udphy_reset_assert(udphy, "init");
> + udphy_reset_assert(udphy, "cmn");
> + udphy_reset_assert(udphy, "lane");
> +
> +assert_apb:
> + udphy_reset_assert(udphy, "pma_apb");
> + udphy_reset_assert(udphy, "pcs_apb");
> +
> + return ret;
> +}
> +
> +static const char * const rk3588_udphy_rst_l[] = {
> + "init", "cmn", "lane", "pcs_apb", "pma_apb"
> +};
> +
> +static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
> + .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
> + .rst_list = rk3588_udphy_rst_l,
> + .grfcfg = {
> + /* u2phy-grf */
> + .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 },
> + .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 },
> +
> + /* usb-grf */
> + .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 },
> + .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 },
> +
> + /* usbdpphy-grf */
> + .low_pwrn = { 0x0004, 13, 13, 0, 1 },
> + .rx_lfps = { 0x0004, 14, 14, 0, 1 },
> + },
> + .combophy_init = rk3588_udphy_init,
> +};
> +
> +static const struct udevice_id rockchip_udphy_dt_match[] = {
> + {
> + .compatible = "rockchip,rk3588-usbdp-phy",
> + .data = (ulong)&rk3588_udphy_cfgs
> + },
> + { /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(rockchip_udphy_u3_port) = {
> + .name = "rockchip_udphy_u3_port",
> + .id = UCLASS_PHY,
> + .ops = &rockchip_u3phy_ops,
> +};
> +
> +U_BOOT_DRIVER(rockchip_udphy) = {
> + .name = "rockchip_udphy",
> + .id = UCLASS_PHY,
> + .of_match = rockchip_udphy_dt_match,
> + .probe = rockchip_udphy_probe,
> + .bind = rockchip_udphy_bind,
> + .priv_auto = sizeof(struct rockchip_udphy),
> +};
> diff --git a/include/linux/usb/phy-rockchip-usbdp.h b/include/linux/usb/phy-rockchip-usbdp.h
> new file mode 100644
> index 000000000000..8acfa6ddf5a3
> --- /dev/null
> +++ b/include/linux/usb/phy-rockchip-usbdp.h
> @@ -0,0 +1,70 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Rockchip USBDP Combo PHY with Samsung IP block driver
> + *
> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __PHY_ROCKCHIP_USBDP_H_
> +#define __PHY_ROCKCHIP_USBDP_H_
> +
> +#include <linux/bitops.h>
> +
> +/* RK3588 USBDP PHY Register Definitions */
> +
> +#define UDPHY_PCS 0x4000
> +#define UDPHY_PMA 0x8000
> +
> +/* VO0 GRF Registers */
> +#define RK3588_GRF_VO0_CON0 0x0000
> +#define RK3588_GRF_VO0_CON2 0x0008
> +#define DP_SINK_HPD_CFG BIT(11)
> +#define DP_SINK_HPD_SEL BIT(10)
> +#define DP_AUX_DIN_SEL BIT(9)
> +#define DP_AUX_DOUT_SEL BIT(8)
> +#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))
> +#define DP_LANE_SEL_ALL GENMASK(7, 0)
> +#define PHY_AUX_DP_DATA_POL_NORMAL 0
> +#define PHY_AUX_DP_DATA_POL_INVERT 1
> +
> +/* PMA CMN Registers */
> +#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
> +#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4)
> +#define CMN_DP_LANE_EN_N(n) BIT(n)
> +#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)
> +#define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
> +#define PHY_LANE_MUX_USB 0
> +#define PHY_LANE_MUX_DP 1
> +
> +#define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */
> +#define CMN_DP_TX_LINK_BW GENMASK(6, 5)
> +#define CMN_DP_TX_LANE_SWAP_EN BIT(2)
> +
> +#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
> +#define CMN_ROPLL_SSC_EN BIT(1)
> +#define CMN_LCPLL_SSC_EN BIT(0)
> +
> +#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
> +#define CMN_ANA_LCPLL_LOCK_DONE BIT(7)
> +#define CMN_ANA_LCPLL_AFC_DONE BIT(6)
> +
> +#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
> +#define CMN_ANA_ROPLL_LOCK_DONE BIT(1)
> +#define CMN_ANA_ROPLL_AFC_DONE BIT(0)
> +
> +#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */
> +#define CMN_DP_INIT_RSTN BIT(3)
> +#define CMN_DP_CMN_RSTN BIT(2)
> +#define CMN_CDR_WTCHDG_EN BIT(1)
> +#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0)
> +
> +#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */
> +#define LN_ANA_TX_SER_TXCLK_INV BIT(1)
> +
> +#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */
> +#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
> +
> +#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */
> +#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0)
> +
> +#endif
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] ARM: dts: rockchip: rk3588: add support for USB 3.0 devices
2023-05-29 10:01 ` [PATCH 2/4] ARM: dts: rockchip: rk3588: add support for USB 3.0 devices Eugen Hristev
@ 2023-07-26 7:35 ` Kever Yang
0 siblings, 0 replies; 9+ messages in thread
From: Kever Yang @ 2023-07-26 7:35 UTC (permalink / raw)
To: Eugen Hristev, u-boot, jonas, jagan; +Cc: Joseph Chen
On 2023/5/29 18:01, Eugen Hristev wrote:
> From: Joseph Chen <chenjh@rock-chips.com>
>
> Add support for the USB 3.0 devices in rk3588:
> - USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in
> rk3588s
> - USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in
> rk3588 only
> - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface
> as usbdp_phy0
> - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface
> as usbdp_phy1
> - USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0
> mode
> - associated GRFs (general register files) for the devices.
>
> Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
> [eugen.hristev@collabora.com: move nodes to right place, adapt from latest
> linux kernel]
> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3588-u-boot.dtsi | 93 +++++++++++++++++++++++++++
> arch/arm/dts/rk3588s-u-boot.dtsi | 105 +++++++++++++++++++++++++++++++
> 2 files changed, 198 insertions(+)
>
> diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
> index 4c8ac804d615..68b419f3abd5 100644
> --- a/arch/arm/dts/rk3588-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-u-boot.dtsi
> @@ -5,3 +5,96 @@
>
> #include "rockchip-u-boot.dtsi"
> #include "rk3588s-u-boot.dtsi"
> +
> +/ {
> + usbdrd3_1: usbdrd3_1 {
> + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
> + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
> + <&cru ACLK_USB3OTG1>;
> + clock-names = "ref", "suspend", "bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usbdrd_dwc3_1: usb@fc400000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0xfc400000 0x0 0x400000>;
> + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&power RK3588_PD_USB>;
> + resets = <&cru SRST_A_USB3OTG1>;
> + reset-names = "usb3-otg";
> + dr_mode = "host";
> + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
> + phy-names = "usb2-phy", "usb3-phy";
> + phy_type = "utmi_wide";
> + snps,dis_enblslpm_quirk;
> + snps,dis-u2-freeclk-exists-quirk;
> + snps,dis-del-phy-power-chg-quirk;
> + snps,dis-tx-ipgap-linecheck-quirk;
> + };
> + };
> +
> + usbdpphy1_grf: syscon@fd5cc000 {
> + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
> + reg = <0x0 0xfd5cc000 0x0 0x4000>;
> + };
> +
> + usb2phy1_grf: syscon@fd5d4000 {
> + compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> + "simple-mfd";
> + reg = <0x0 0xfd5d4000 0x0 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + u2phy1: usb2-phy@4000 {
> + compatible = "rockchip,rk3588-usb2phy";
> + reg = <0x4000 0x10>;
> + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
> + reset-names = "phy", "apb";
> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> + clock-names = "phyclk";
> + clock-output-names = "usb480m_phy1";
> + #clock-cells = <0>;
> + rockchip,usbctrl-grf = <&usb_grf>;
> + status = "disabled";
> +
> + u2phy1_otg: otg-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + usbdp_phy1: phy@fed90000 {
> + compatible = "rockchip,rk3588-usbdp-phy";
> + reg = <0x0 0xfed90000 0x0 0x10000>;
> + rockchip,u2phy-grf = <&usb2phy1_grf>;
> + rockchip,usb-grf = <&usb_grf>;
> + rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
> + rockchip,vo-grf = <&vo0_grf>;
> + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
> + <&cru CLK_USBDP_PHY1_IMMORTAL>,
> + <&cru PCLK_USBDPPHY1>,
> + <&u2phy1>;
> + clock-names = "refclk", "immortal", "pclk", "utmi";
> + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
> + <&cru SRST_USBDP_COMBO_PHY1_CMN>,
> + <&cru SRST_USBDP_COMBO_PHY1_LANE>,
> + <&cru SRST_USBDP_COMBO_PHY1_PCS>,
> + <&cru SRST_P_USBDPPHY1>;
> + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
> + status = "disabled";
> +
> + usbdp_phy1_dp: dp-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + usbdp_phy1_u3: usb3-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> +};
> diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
> index 1bb3c6a9d958..acb1cfe20063 100644
> --- a/arch/arm/dts/rk3588s-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588s-u-boot.dtsi
> @@ -13,6 +13,37 @@
> status = "okay";
> };
>
> + usbdrd3_0: usbdrd3_0 {
> + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
> + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
> + <&cru ACLK_USB3OTG0>;
> + clock-names = "ref", "suspend", "bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usbdrd_dwc3_0: usb@fc000000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0xfc000000 0x0 0x400000>;
> + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&power RK3588_PD_USB>;
> + resets = <&cru SRST_A_USB3OTG0>;
> + reset-names = "usb3-otg";
> + dr_mode = "otg";
> + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
> + phy-names = "usb2-phy", "usb3-phy";
> + phy_type = "utmi_wide";
> + snps,dis_enblslpm_quirk;
> + snps,dis-u1-entry-quirk;
> + snps,dis-u2-entry-quirk;
> + snps,dis-u2-freeclk-exists-quirk;
> + snps,dis-del-phy-power-chg-quirk;
> + snps,dis-tx-ipgap-linecheck-quirk;
> + quirk-skip-phy-init;
> + };
> + };
> +
> usb_host0_ehci: usb@fc800000 {
> compatible = "generic-ehci";
> reg = <0x0 0xfc800000 0x0 0x40000>;
> @@ -64,6 +95,33 @@
> reg = <0x0 0xfd5bc000 0x0 0x100>;
> };
>
> + usb2phy0_grf: syscon@fd5d0000 {
> + compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> + "simple-mfd";
> + reg = <0x0 0xfd5d0000 0x0 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + u2phy0: usb2-phy@0 {
> + compatible = "rockchip,rk3588-usb2phy";
> + reg = <0x0 0x10>;
> + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
> + reset-names = "phy", "apb";
> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> + clock-names = "phyclk";
> + clock-output-names = "usb480m_phy0";
> + #clock-cells = <0>;
> + rockchip,usbctrl-grf = <&usb_grf>;
> + status = "disabled";
> +
> + u2phy0_otg: otg-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> + };
> +
> usb2phy2_grf: syscon@fd5d8000 {
> compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> "simple-mfd";
> @@ -87,6 +145,17 @@
> };
> };
>
> + vo0_grf: syscon@fd5a6000 {
> + compatible = "rockchip,rk3588-vo-grf", "syscon";
> + reg = <0x0 0xfd5a6000 0x0 0x2000>;
> + clocks = <&cru PCLK_VO0GRF>;
> + };
> +
> + usb_grf: syscon@fd5ac000 {
> + compatible = "rockchip,rk3588-usb-grf", "syscon";
> + reg = <0x0 0xfd5ac000 0x0 0x4000>;
> + };
> +
> usb2phy3_grf: syscon@fd5dc000 {
> compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> "simple-mfd";
> @@ -110,6 +179,11 @@
> };
> };
>
> + usbdpphy0_grf: syscon@fd5c8000 {
> + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
> + reg = <0x0 0xfd5c8000 0x0 0x4000>;
> + };
> +
> pcie2x1l2: pcie@fe190000 {
> compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
> #address-cells = <3>;
> @@ -180,6 +254,37 @@
> status = "disabled";
> };
>
> + usbdp_phy0: phy@fed80000 {
> + compatible = "rockchip,rk3588-usbdp-phy";
> + reg = <0x0 0xfed80000 0x0 0x10000>;
> + rockchip,u2phy-grf = <&usb2phy0_grf>;
> + rockchip,usb-grf = <&usb_grf>;
> + rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
> + rockchip,vo-grf = <&vo0_grf>;
> + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
> + <&cru CLK_USBDP_PHY0_IMMORTAL>,
> + <&cru PCLK_USBDPPHY0>,
> + <&u2phy0>;
> + clock-names = "refclk", "immortal", "pclk", "utmi";
> + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
> + <&cru SRST_USBDP_COMBO_PHY0_CMN>,
> + <&cru SRST_USBDP_COMBO_PHY0_LANE>,
> + <&cru SRST_USBDP_COMBO_PHY0_PCS>,
> + <&cru SRST_P_USBDPPHY0>;
> + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
> + status = "disabled";
> +
> + usbdp_phy0_dp: dp-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + usbdp_phy0_u3: usb3-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> +
> combphy0_ps: phy@fee00000 {
> compatible = "rockchip,rk3588-naneng-combphy";
> reg = <0x0 0xfee00000 0x0 0x100>;
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support
2023-05-29 10:01 ` [PATCH 3/4] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support Eugen Hristev
@ 2023-07-26 7:36 ` Kever Yang
0 siblings, 0 replies; 9+ messages in thread
From: Kever Yang @ 2023-07-26 7:36 UTC (permalink / raw)
To: Eugen Hristev, u-boot, jonas, jagan
On 2023/5/29 18:01, Eugen Hristev wrote:
> Enable the USB3.0 host node, and gadget node.
> The gadget is available through the USB type C connector on the board.
> The connector is tied to a Fairchild fusb302b device, which currently
> does not have a driver in U-boot, but the node is here for correct
> description of the board + Linux future compatibility.
> It will be easier to move the node as-is when it will be available
> in the DT from Linux
>
> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 197 ++++++++++++++++++++++++
> 1 file changed, 197 insertions(+)
>
> diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> index 1cd8a57a6fa6..5a3292699640 100644
> --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/pinctrl/rockchip.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/usb/pd.h>
>
> / {
> aliases {
> @@ -18,6 +19,25 @@
> u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
> };
>
> + vcc12v_dcin: vcc12v-dcin-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc12v_dcin";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + };
> +
> + vcc5v0_usbdcin: vcc5v0-usbdcin {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_usbdcin";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc12v_dcin>;
> + };
> +
> vcc5v0_host: vcc5v0-host-regulator {
> compatible = "regulator-fixed";
> regulator-name = "vcc5v0_host";
> @@ -29,6 +49,28 @@
> pinctrl-0 = <&vcc5v0_host_en>;
> vin-supply = <&vcc5v0_sys>;
> };
> +
> + vcc5v0_usb: vcc5v0-usb {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_usb";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc5v0_usbdcin>;
> + };
> +
> + vbus5v0_typec: vbus5v0-typec {
> + compatible = "regulator-fixed";
> + regulator-name = "vbus5v0_typec";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
> + vin-supply = <&vcc5v0_usb>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&typec5v_pwren>;
> + };
> };
>
> &combphy0_ps {
> @@ -85,6 +127,16 @@
> rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
> +
> + usb-typec {
> + usbc0_int: usbc0-int {
> + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> +
> + typec5v_pwren: typec5v-pwren {
> + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> };
>
> &pcfg_pull_none {
> @@ -168,6 +220,15 @@
> status = "okay";
> };
>
> +&u2phy0 {
> + status = "okay";
> +};
> +
> +&u2phy0_otg {
> + rockchip,typec-vbus-det;
> + status = "okay";
> +};
> +
> &u2phy2 {
> resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
> reset-names = "phy", "apb";
> @@ -209,3 +270,139 @@
> status = "okay";
> };
>
> +&usbdp_phy0 {
> + orientation-switch;
> + svid = <0xff01>;
> + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
> + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + usbdp_phy0_orientation_switch: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&usbc0_orien_sw>;
> + };
> +
> + usbdp_phy0_dp_altmode_mux: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&dp_altmode_mux>;
> + };
> + };
> +};
> +
> +&usbdp_phy0_u3 {
> + status = "okay";
> +};
> +
> +&usbdrd3_0 {
> + status = "okay";
> +};
> +
> +&usbdrd_dwc3_0 {
> + dr_mode = "otg";
> + usb-role-switch;
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + dwc3_0_role_switch: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&usbc0_role_sw>;
> + };
> + };
> +};
> +
> +&usbdp_phy1 {
> + rockchip,dp-lane-mux = <2 3>;
> + status = "okay";
> +};
> +
> +&usbdp_phy1_u3 {
> + status = "okay";
> +};
> +
> +&usbdrd3_1 {
> + status = "okay";
> +};
> +
> +&u2phy1 {
> + status = "okay";
> +};
> +
> +&u2phy1_otg {
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-0 = <&i2c4m1_xfer>;
> + status = "okay";
> +
> + usbc0: fusb302@22 {
> + compatible = "fcs,fusb302";
> + reg = <0x22>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&usbc0_int>;
> + vbus-supply = <&vbus5v0_typec>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + usbc0_role_sw: endpoint@0 {
> + remote-endpoint = <&dwc3_0_role_switch>;
> + };
> + };
> + };
> +
> + usb_con: connector {
> + compatible = "usb-c-connector";
> + label = "USB-C";
> + data-role = "dual";
> + power-role = "dual";
> + try-power-role = "sink";
> + op-sink-microwatt = <1000000>;
> + sink-pdos =
> + <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
> + source-pdos =
> + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
> +
> + altmodes {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + altmode@0 {
> + reg = <0>;
> + svid = <0xff01>;
> + vdo = <0xffffffff>;
> + };
> + };
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + usbc0_orien_sw: endpoint {
> + remote-endpoint = <&usbdp_phy0_orientation_switch>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dp_altmode_mux: endpoint {
> + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
> + };
> + };
> + };
> + };
> + };
> +};
> +
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget
2023-05-29 10:01 ` [PATCH 4/4] configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget Eugen Hristev
@ 2023-07-26 7:36 ` Kever Yang
0 siblings, 0 replies; 9+ messages in thread
From: Kever Yang @ 2023-07-26 7:36 UTC (permalink / raw)
To: Eugen Hristev, u-boot, jonas, jagan
On 2023/5/29 18:01, Eugen Hristev wrote:
> Enable configuration for USB 3.0 controller, the commands required,
> and the gadget drivers.
>
> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> configs/rock5b-rk3588_defconfig | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
> index a4a3c0afd178..3f28a68f0c94 100644
> --- a/configs/rock5b-rk3588_defconfig
> +++ b/configs/rock5b-rk3588_defconfig
> @@ -47,9 +47,11 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
> CONFIG_SPL_ATF=y
> CONFIG_CMD_GPIO=y
> CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> CONFIG_CMD_MMC=y
> CONFIG_CMD_PCI=y
> CONFIG_CMD_USB=y
> +CONFIG_CMD_ROCKUSB=y
> # CONFIG_CMD_SETEXPR is not set
> CONFIG_CMD_REGULATOR=y
> # CONFIG_SPL_DOS_PARTITION is not set
> @@ -59,6 +61,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
> CONFIG_SPL_REGMAP=y
> CONFIG_SPL_SYSCON=y
> CONFIG_SPL_CLK=y
> +# CONFIG_USB_FUNCTION_FASTBOOT is not set
> CONFIG_ROCKCHIP_GPIO=y
> CONFIG_SYS_I2C_ROCKCHIP=y
> CONFIG_MISC=y
> @@ -76,6 +79,7 @@ CONFIG_GMAC_ROCKCHIP=y
> CONFIG_PCIE_DW_ROCKCHIP=y
> CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
> +CONFIG_PHY_ROCKCHIP_USBDP=y
> CONFIG_SPL_PINCTRL=y
> CONFIG_REGULATOR_PWM=y
> CONFIG_PWM_ROCKCHIP=y
> @@ -86,10 +90,16 @@ CONFIG_SYS_NS16550_MEM32=y
> CONFIG_ROCKCHIP_SFC=y
> CONFIG_SYSRESET=y
> CONFIG_USB=y
> +CONFIG_DM_USB_GADGET=y
> +CONFIG_USB_XHCI_HCD=y
> +# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_EHCI_GENERIC=y
> CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
> +CONFIG_SPL_USB_DWC3_GENERIC=y
> CONFIG_USB_HOST_ETHER=y
> CONFIG_USB_ETHER_ASIX=y
> CONFIG_USB_ETHER_ASIX88179=y
> @@ -98,4 +108,8 @@ CONFIG_USB_ETHER_LAN78XX=y
> CONFIG_USB_ETHER_MCS7830=y
> CONFIG_USB_ETHER_RTL8152=y
> CONFIG_USB_ETHER_SMSC95XX=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_PRODUCT_NUM=0x350b
> +CONFIG_USB_GADGET_DOWNLOAD=y
> +CONFIG_USB_FUNCTION_ROCKUSB=y
> CONFIG_ERRNO_STR=y
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-07-26 7:37 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-05-29 10:01 [PATCH 0/4] rockchip: rk3588: add USB 3.0 support Eugen Hristev
2023-05-29 10:01 ` [PATCH 1/4] phy: rockchip: add usbdp combo phy driver Eugen Hristev
2023-07-26 7:29 ` Kever Yang
2023-05-29 10:01 ` [PATCH 2/4] ARM: dts: rockchip: rk3588: add support for USB 3.0 devices Eugen Hristev
2023-07-26 7:35 ` Kever Yang
2023-05-29 10:01 ` [PATCH 3/4] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support Eugen Hristev
2023-07-26 7:36 ` Kever Yang
2023-05-29 10:01 ` [PATCH 4/4] configs: rock5b-rk3588: enable USB 3.0 controller, command, gadget Eugen Hristev
2023-07-26 7:36 ` Kever Yang
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