From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3E38C7EE2E for ; Mon, 12 Jun 2023 20:11:41 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7CC9085F4F; Mon, 12 Jun 2023 22:11:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 76B0F86131; Mon, 12 Jun 2023 22:11:38 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 8B1D085F29 for ; Mon, 12 Jun 2023 22:11:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE0301FB; Mon, 12 Jun 2023 13:12:19 -0700 (PDT) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4D8793F5A1; Mon, 12 Jun 2023 13:11:34 -0700 (PDT) Date: Mon, 12 Jun 2023 01:20:56 +0100 From: Andre Przywara To: Sam Edwards Cc: u-boot@lists.denx.de Subject: Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Message-ID: <20230612012056.65883683@slackpad.lan> In-Reply-To: <04c52801-a6d0-033b-c7f4-613e0b789d96@gmail.com> References: <20221206004549.29015-1-andre.przywara@arm.com> <04c52801-a6d0-033b-c7f4-613e0b789d96@gmail.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.1 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Fri, 9 Jun 2023 16:16:43 -0600 Sam Edwards wrote: Hi Sam, > On 12/5/22 17:45, Andre Przywara wrote: > > Please let me know if you have any opinions! =20 >=20 > I believe I promised you last month I'd let you know once I had a build=20 > I'm happy with, and I'm pleased to say that I think I've reached that=20 > point. I'm running quite rapidly out of sharp edges to sand down, too. Thanks for the update and the list! Can you confirm where you still needed code changes compared to say my github branch plus the changes we already discussed? Trying some guesses below, please confirm or deny: > I have a build of U-Boot for my target, complete with: > - UART3 initialized correctly this is problematic because of the other pinmux used on your board, which cannot easily be encoded alongside the existing UART3 pinmux? > - DRAM coming up correctly > - SPL sets configured boot clock correctly This should work as per github? > - SPI-NAND support (SPL and U-Boot proper) This is with Icenow's series? Any D1 specific changes needed there? > - MMC support (SPL and U-Boot proper) > - SPL boot from FEL again worked already in github? > - USB gadget support So with the fixed SUNXI_SRAMC_BASE you said it worked? What about the USB PHY? That needs at least wiring in the compatible string? If you have such a patch, can you please rebase it on top of my v2 USB PHY series and post that? > - Ethernet MAC+PHY support Anything surprising here? Is that using an already supported external PHY? > - I=C2=B2C support * > - GPIO support (LEDs, buttons, misc. board management) again should work out of the box, minus your board specific configuration? > - `reset` working (requries CONFIG_SYSRESET unset, WDT key) Isn't "CONFIG_SYSRESET unset" a hack? I dimly remember we had this for some other SoC initially, but later got rid of it? For the WDT key: it seems like Linux got a nice patch to integrate this neatly into the driver without quirking this too much, do you have something ready for U-Boot as well? Would love to see it on the list then ;-) > - PSCI, nonsec ah yeah, owe you some reviews on this one ... > - Able to boot Linux ;) >=20 > * Requires nonzero `MVTWSI_CONTROL_CLEAR_IFLG` for NCAT2, and a patch to= =20 > the pinctrl driver to configure the proper mux function for my necessary= =20 > pins. Are those pinmuxes straight forward to add to the pinctrl driver? Or are there conflicts similar to UART3? =20 > I figured I'd share this list as a sort of checklist for your own work,=20 > too. The remainder of my efforts now will probably be focused on=20 > mainlining this stuff (let me know how else I can be of help), and then=20 > I'm afraid I'll have to disappear back downstream to the Turing Pi 2=20 > development effort, but maybe our paths will cross again in the kernel=20 > lists. :) Yeah, as you may know, the DT has to go through the kernel list. DT patches can be tedious to upstream, there is now much attention to every detail. Running checkpatch and dtbs_check should reveal most issues beforehand, though. Cheers, Andre >=20 > Thank you greatly, > Sam >=20 > P.S. I figure the reason there aren't I=C2=B2C function defs in the d1=20 > pinctrl table already is because Allwinner tends to kick around the I=C2= =B2C=20 > mux values a lot and we would need a per-pin lookup table that would eat= =20 > up too much valuable image space? >=20 > In an entirely JUST FOR FUN exercise to give myself a break from staring= =20 > at datasheets/patches and do a "pure CS" coding challenge for a change,=20 > I came up with a terse encoding scheme for this table. Here is the size=20 > (in bits) for a selection of D1's functions (pin assignments harvested=20 > from Linux): >=20 > 'emac': 50, > 'i2c0': 101, > 'i2c1': 64, > 'i2c2': 109, > 'i2c3': 91, > 'mmc0': 23, > 'mmc1': 23, > 'mmc2': 20, > 'spi0': 41, > 'spi1': 48, > 'uart0': 78, > 'uart1': 87, > 'uart2': 88, > 'uart3': 102, > 'uart4': 68, > 'uart5': 66, >=20 > ...and yes, it also identifies invalid pin assignments! I'd be willing=20 > to contribute something like this if there's big interest, but I figure=20 > needing to compress this at build-time might be a bit too complicated=20 > for the U-Boot project's liking.